Clawhammer: Clearing A Narrow Path? . . .

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AMD has essentially gotten first silicon out on Clawhammer and demonstrated it at IDF. It’s not up to speed and nowhere near ready yet, which
is no big deal for a processor/chipset that isn’t supposed to be out until the end of the year. Just don’t expect it before then.

What is troubling, and more than a bit confusing, are the memory arrangements.

AMD did a dog-and-pony show on these processors.

The Hammer processor core includes a DDR memory controller, which is supposed to quicken things up. It supports up to PC2700, which makes me wonder a little what happens when we go beyond PC2700.

Of more immediate concern is just how much is getting controlled. The AMD documentation states that the DDR memory controller is either a “single or dual channel DDR memory interface.”

A Pin Cushion

Adding to the uncertainty is the disclosure that Clawhammer and Sledgehammer have a different number of pins. Clawhammer has 754 pins, Sledgehammer will have 930. It’s unclear at this point whether the two could fit in the same socket; the design would seem to indicate it’s at least conceivable.

Just what do they plan to do with all those pins, and what are the extra Sledgehammer pins for?

A lot of them are going to be used for the Hypertransport links between the CPU and either the other system or the other processors. However, not all that many.

The Hammers can have one, two, or three links of up to 6.4Gb bandwidth. However, the maximum 32-bit Hypertransport link takes only 64 pins for the basic implementation. Update 2/28/02: A few people knew or knew where to look better than me, and were kind enough to point out this white paper (page 12). Since it’s not exactly
clear what the bus-width, clock speed, and/or whether the 6.4Gb/sec stated is per direction or the total of both direction, the pin total is either 103 or 197 pins per link.

Presuming AMD is using that, it’s hard to see how you get two additional Hypertransport links and an additional 64-bit memory channel out of an extra 176 pins.

Then again, when almost three hundred pins get added to the “base” model; you have some room to work with.

I would suspect that those 754 pins all by themselves cover more than just a single-channel memory controller and one Hypertransport link.

If AMD seriously wants to keep and expands the inroads it’s made into the workstation market, it had better plan to have Clawhammers uses both memory controllers, and sooner rather than later. Otherwise, it hands an advantage to Intel, which will have a dual DDR setup by the time Clawhammer comes out.

MHz Malaise

Some of you only think you hate PR now. Just wait until Clawhammer.

It looks like AMD is going in the opposite direction of Intel when it comes to the processor doing work. Clawhammer is supposed to do 30% more work per clock cycle than an Athlon. So it’s likely the first Clawhammer will actually run at something like 2GHz and get a PR rating of 3400+.

Though PR seems to have been swallowed (either knowingly or unknowingly) for the XP, I think that even many of those who swallowed PR for the XP with little fuss won’t may find their credulity stretched to the breaking point when they get told that this processor is “really” almost twice as fast as its “MHz.” Even if it is.

Never mind those who never accepted it in the first place.

That will certainly be a major problem AMD will have to contend with.

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