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Originally posted by PCphreak
It's surprising to see how many people do not understand how memory bandwidth and a data bus correlate. I explained this in his other thread, while not thoroughly- because of the complexity of the issue; I did explain enough to show the benefits of nForce2. Of course the benefits only come when nForce2 is not running @ spec. I'll quote my post below:
To get a full grasp on bandwidth and memory throughput, you need to understand it.
Right now DIMMs, whether SDR or DDR, are 64 bit's wide. This is important to note, because the CPU's external bus interface is 64-bits wide also. This is also why we are able to add memory a single DIMM at a time, whereas older SIMMS (32-bits wide) had to be added in pairs to match the CPU's external 64-bit bus interface.
The FSB and memory bus are two different busses, but must cooperatively operate together. They operate together more efficiently when their cycle time is lower and synchronous. As clock speed increases cycle time decreases. Example: a 2 GHz CPU cycles every .5 ns, while a DDR 400 bus cycles every 2.5 ns (ns = nanoseconds). ( 1 / MHz * 1000 = ns).
So what happens when a 2 GHz processor trys to directly access a DDR 400 bus? About 4.5 wait states (blank cycle CPU executes) till data is ready for the CPU on the DDR 400 bus's next event cycle. These wait states effectively slow down the CPU from 2 GHz to the 400 MHz of the bus. Same principle goes for any bus working together. Now you can see why it's important to run synchronous rather than async which introduces bottle necks.
I'm not going to get into the latency of memory, which is the time involved in a setting up a transfer. So I'll move on to bandwidth.
Memory bandwidth is figured by this:
(Bus Width) multiplied by (Clock Speed), and this product multiplied by (Data Cycles Per Clock).
Example: The Athlon's FSB is 64-bits wide and runs at clock speed 133 MHz and manages 2 data cycles per clock. This works out to be
( 8 bytes(64-bits) * 133 MHz * 2 = 2,128 MB/s ), or approx. 2.1 GB/s. To take full advantage of the FSB's bandwidth, you'd need to pair it with memory at the same bandwidth. DDR 2100 does this exactly. ( 8 * 133 MHz * 2 = 2,128 MB/s ). Or ( 8 * 266 MHz = 2,128 MB/s ); however you want to figure it.
Now you have it. Since Athlon is based on a DDR bus, it's better paired with DDR memory to directly match it. Remember, the higher the clock speed of the FSB the closer it's cycle time is to the CPU and less wait states occur in the event of a L2 cache miss.
As far as the P4 goes, it has a 128-byte line size and runs on a quad based bus (high bandwidth; 8 (64-bits) x 133 MHz x 4 = 4,256 MB/s ). So naturally it will benefit from a memory bus able to match. Right now, stock, Dual DDR 400 is right up it's ally.
I hope this helps a bit, as I spent some time typing this.
*note*
1) A CPU will only access memory directly if the cache controller misses, and data needed isn't present in L2 cache.
2)The 'memory bandwidth' example for the AMD is illustrated @ stock specs. Naturally bandwidth is a direct function of clock speed- the higher the clock the greater the bandwidth.
-PC
unwrittenLaw said:
CI buses, run memory at a stable speed (since memory has its own clock generator) put the fsb at max, and lower the multi till it's stable, and even if the multi causes the proc to go to a stock speed (XP 2400 @ 333x6 = 2GHz) the high fsb is definitely worth it.
