Hyper transport bus of the opteron/64

ok, i was reading on the AMD site about the hyper-trnasport bus. It said they have it at 800Mhz. Is that their new fancy term for the front side bus or is it a different bus completely? If so is it quad pumped like the P4's to get it at 800 or just 400DDR?

just curiose, if you have answeres, great if not, thats ok.
TIA
-f1

From my understanding...

There is no traditional front side bus with the Opteron / Athlon64 since the memory controller is built into the cpu core. Hyper transport is a 16 bit wide bus with 3.2GB/sec transfers in each direction (up to 6.4 total). One of these buses is used for pci, agp and other southbridge i/o. Note that without memory transactions, this bus will have much less traffic than a traditional front side bus.

The Opteron has up to three of these 3.2 GB/sec hyper transport links. In the 8xx series chips all three are enabled with two used for cpu to cpu communications in up to 8-way configurations without needing a chipset in between the individual processors.

It is also rumored that the hyper transport protocol is close enough to pci express that the inclusion of pci express should be relatively simple in future motherboard designs.

Anandtech has a multipart series on the Opteron which you might find interesting:
http://anandtech.com/cpu/showdoc.html?i=1815

The AMD hyper-transport is mainly to deal with peripheral subsystems such as networking, storage such as external and internal hard drives, serial links such as USB, firewire, ...

http://www.amd.com/us-en/Processors/DevelopWithAMD/0,,30_2252_2353,00.html

Don't confuse it with the FSB which is between the processor, north bridge and the memory controller, though eventually, would become part of the processor chip.

thanck for the replys! i checked out those links and i pretty much get it now. thanks again!

hitechjb1 said:

The AMD hyper-transport is mainly to deal with peripheral subsystems such as networking, storage such as external and internal hard drives, serial links such as USB, firewire, ...

http://www.amd.com/us-en/Processors/DevelopWithAMD/0,,30_2252_2353,00.html

Don't confuse it with the FSB which is between the processor, north bridge and the memory controller, though eventually, would become part of the processor chip.

Click to expand...

No. The HT bus is also used to control memory through a HT link onboard the processor, attached to the onboard memory controller. There are only a few things that are HT-linked directly to the processor, including AGP, PCI(-X), and memory. The rest (audio, USB, IEEE 1394 etc) are still linked through a southbridge type chip.

There is no Northbridge or FSB or separate memory controller on a K8 system. The advantages of this are similar to moving the cache from off the chip to on die.

www.hypertransport.org/

Hyper Transport is manily for next generation peripheral subsystems such as networking, storage, serial links, ... and chip to chip communication and I/O.

Currently, its specification is 200-800 MHz with DDR, hence max bit rate is 1600 Mb/s (per bit). It is based on packet switching and allows for bi-directional transfer. Data width is 2, 4, 8, 16, 32 bit.

At maximum 32-bit transfer, the max bandwidth would be 32 x 800 x 2 / 8 = 6400 MB/s = 6.4 GB/s. Since transfer is allowed for bi-direction, for 32-bit transfer, the max throughput is up to 12.8 GB/s.

Compared this speed with 33 MHz/32-bit PCI which is 133 MB/s, it is 48X. Compared to the 1 GB/s for PCI-express, it is 12X.

Even the max bandwidth of 6.4 GB/s is comparable to that offered by the current FSB at 200 MHz, quad pump P4 is 6.4 GB/s or DDR for AMD is 3.2 GB/s. HT is for chip to chip, and chip to peripheral communication, not for system memory which has a data path of 64/128 bit, is connected to the memory controller (which will on on the processor chip for next generation processor), and using a different communication protocol, ...


Hyper transport FAQ
http://www.hypertransport.org/faqs.html

http://www.hypertransport.org/technology.html