Hyper Transport is manily for next generation peripheral subsystems such as networking, storage, serial links, ... and chip to chip communication and I/O.
Currently, its specification is 200-800 MHz with DDR, hence max bit rate is 1600 Mb/s (per bit). It is based on packet switching and allows for bi-directional transfer. Data width is 2, 4, 8, 16, 32 bit.
At maximum 32-bit transfer, the max bandwidth would be 32 x 800 x 2 / 8 = 6400 MB/s = 6.4 GB/s. Since transfer is allowed for bi-direction, for 32-bit transfer, the max throughput is up to 12.8 GB/s.
Compared this speed with 33 MHz/32-bit PCI which is 133 MB/s, it is 48X. Compared to the 1 GB/s for PCI-express, it is 12X.
Even the max bandwidth of 6.4 GB/s is comparable to that offered by the current FSB at 200 MHz, quad pump P4 is 6.4 GB/s or DDR for AMD is 3.2 GB/s. HT is for chip to chip, and chip to peripheral communication, not for system memory which has a data path of 64/128 bit, is connected to the memory controller (which will on on the processor chip for next generation processor), and using a different communication protocol, ...
Hyper transport FAQ
http://www.hypertransport.org/faqs.html
http://www.hypertransport.org/technology.html