amd axia`s

[littlerichie]

i just was scanning another website and it stated
that a quote from a former employee.
that the athlon (t-bird`s) axia codes where erroneosly
shipped by mistake.
the axia`s are actually the palomino`s 1.5 ghz
chips that were supposed to be shipped to a testing
facility.
david

[kat]

two completly different chips ;D

[Megahurtz]

As the die sizes differ, they cannot be the same..It is now your duty to go correct the errant post. I have an AXIA, and it is 'physically' the same as all the other Socket-A T-birds.

T

[littlerichie]

Megahurtz (Apr 16, 2001 05:21 p.m.):
As the die sizes differ, they cannot be the same..It is now your duty to go correct the errant post. I have an AXIA, and it is 'physically' the same as all the other Socket-A T-birds.

T
ah! excuse me !
it was not an error on my part?
i simply restated what the statement was from the other website.
in addition to that the axia`s use .12 micron
technology.
p.s. read carefully before you assume.
david

[kat]

im not sure littlerichie
but i think Megahurtz was suggesting you go to where you read the rumor and tell them the real deal ;D

About the AMD Athlon Processor
The AMD Athlon processor is an x86-compatible, seventh-generation design featuring a superpipelined, nine-issue superscalar microarchitecture optimized for high clock frequency; the industry's first fully pipelined, superscalar floating point unit for x86 platforms; high-performance cache architecture, now featuring 384KB of total on-chip cache (256KB of on-chip level (L2) cache and 128KB of on-chip level (L1) cache); enhanced 3DNow!™ technology with 24 additional instructions designed to improve integer math calculations, data movement for Internet streaming, and DSP communications. The AMD Athlon processor features either a 266MHz Front Side Bus (FSB) or a 200MHz FSB based on the Alpha™ EV6 bus protocol. AMD Athlon processors are manufactured using AMD's 0.18-micron process technology in Fab 25 in Austin, Texas and AMD's 0.18 micron copper process technology in Fab 30 in Dresden, Germany.

[Big Mike]

As I remember the Palomino early pics that were up on uh...well I don't remember the site showed that the chip had 5 L1 bridges instead of 4 and a number of extra bridges on the other L#s...as far as i know AXIAs are all standard 4 L1 chips etc etc

[Megahurtz]

ah! excuse me !
it was not an error on my part?
i simply restated what the statement was from the other website.
in addition to that the axia`s use .12 micron
technology.
p.s. read carefully before you assume.
david

Awfully sorry about that bit of confusion. Kat assessed my post as I intended. I know that you came here seeking facts. I meant for my post be a light-hearted one. Once again my feeble attempt a humor has fallen short.

No hard feelings,

T

[kat]

Megahurtz (Apr 17, 2001 07:59 p.m.):
ah! excuse me !
it was not an error on my part?
i simply restated what the statement was from the other website.
in addition to that the axia`s use .12 micron
technology.
p.s. read carefully before you assume.
david

Awfully sorry about that bit of confusion. Kat assessed my post as I intended. I know that you came here seeking facts. I meant for my post be a light-hearted one. Once again my feeble attempt a humor has fallen short.

No hard feelings,

T

:) its hard to tell what a person is thinking on the forum :-D the little face`s will help ;-) if you choose not to use them because you are to 8) then you face the unavoidible problem of getting every one`s shorts in a knot ???