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What is the difference between Palomino & Thoroughbred

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Falseprophet

Member
Joined
Feb 25, 2002
Location
Ogden, Utah, USA
I was just wondering what the difference between the palomino and the Thoroughbred CPU's are. I have a Palomino and I don't know the difference.???
 
palomino = 1.75v default voltage and typically max out around 1.8-1.9ghz. .018 micron

t-bred = 1.50-1.65v and typically max out around 2.2-2.5ghz. .013 micron



Falseprophet said:
I was just wondering what the difference between the palomino and the Thoroughbred CPU's are. I have a Palomino and I don't know the difference.???
 
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hitechjb1 (04-30-2003 04:33 PM) said:
If you can see the chip die physically, as someone already pointed out, palomino is more square shape like and the Tbred A and B are more rectangular like.

The palomino are bigger in die size 128 mm^2, compared to 80 and 84 mm^2 for Tbred A and B.

If you can see the transistors and can count them, the palomino has 37.5 million, whereas the Tbred A and B have 37.2 and 37.6 millions respectively.

If your eye is powerful enough and able to go inside the chip and see the transistors, the palomino transistors have a width of 0.18 micron and whereas the Tbred transistors have a width of 0.13 micron.

If you are able to count the number of metal wires, the palomino has 7 layers, whereas Tbred A has 8 layers and Tbred B has 9 layers.

OK, back to business. Since we probably can't see these with our naked eyes, ...

But if the chip is already covered by the HSF, and you cannot see the die shape, the stepping, ... This is the trick to find out:

Palomino has only one default Vcore of 1.75V. Tbred A and Tbred B has multiple default Vcore of 1.5 (the famous 1700+ DLT3C), 1.6 and 1.65 V depends on the PR rating of the Tbred.

You can get into the bios, set the Vcore to default.

If it says 1.75 V then it is a palomino.

If it is 1.5 or 1.6 or 1.65 V, it is a Tbred A or B.


A more interesting question is why Tbred B, in particular the Tbred B DLT3C, being rated at lower Vcore but it can run faster than other Tbred B at same voltage. The main reason I think is due to lower transistor threshold and shorter channel length. Even it is manufactured with 0.13 micron like other Tbred B, it is effectively behaving like a chip with less than 0.13 micron, if you like.

link: Why the 1700+ can run so fast at low Vcore?
 
Wow. Where do you guys get all this intresting data. I really enjoyed the post of the specs. when I ordered my 1800+ I don't think that the t-breds were out yet.might be wrong. I was just wondering if they were being rated like (Athelon & Duron) you know, Great and Cheaper. In the next month or two I am going to upgrade my MOBO, CPU, RAM. wanted OCZ dual channel (1024) kit (512x2) pc3200 with heat spreader $290 ouch!!!
 
Yes I think you are right a combination of gate resizing and smaller channel length has meant a reduction in supply voltage meaning increased potential for overclocking. The fact that sub threshold leakage current increases exponentially for a corresponding decrease in threshold voltage (whilst the comparison between a DUT3C and DLT3C is only 7%) means that threshold voltage is not being scaled with supply voltage helped possibly by tighter pmos:nmos ratios?
 
OC Detective said:
Yes I think you are right a combination of gate resizing and smaller channel length has meant a reduction in supply voltage meaning increased potential for overclocking. The fact that sub threshold leakage current increases exponentially for a corresponding decrease in threshold voltage (whilst the comparison between a DUT3C and DLT3C is only 7%) means that threshold voltage is not being scaled with supply voltage helped possibly by tighter pmos:nmos ratios?

The scary thing is that I am on the verge of understanding that :eh?:
 
OC Detective said:
Yes I think you are right a combination of gate resizing and smaller channel length has meant a reduction in supply voltage meaning increased potential for overclocking. The fact that sub threshold leakage current increases exponentially for a corresponding decrease in threshold voltage (whilst the comparison between a DUT3C and DLT3C is only 7%) means that threshold voltage is not being scaled with supply voltage helped possibly by tighter pmos:nmos ratios?

I don't think the nominal p:n ratio of individual transistors in the Tbred B 1700+ DLT3C are any different than the DUT3C and DKT3C Tbred B siblings, and play a role in its relative better speed at same voltage. They are from the same circuit design and wafer mask. So I think the speed gain of the DLT3C is mainly due to reduce in transistor threshold voltage and channel length, a result of process variation. Such deviation is only marginal and is less drastic as an actual change from technology scaling, such as going from 0.18 micron to 0.13 micro to 0.09 micron.

The sub-threshold leakage current increase due to process variation (say 5-10% threshold voltage), though exponential in nature with voltage and temperature, would be much smaller (say 12-26% estimated). Further such leakage current, I estimated, is around 10-15% of the total CPU current. As a result, the increase in leakage current is estimated to be 1-4% (within the 7% higher current I quoted from the spec for the 1700+ DLT3C) of the total chip current.
 
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I meant the potential tightening of the p:n ratio may have helped in limiting the exponential factor of the sub threshold leakage current rather than it helping in the higher clock speeds. The higher clock speeds come from the gate resizing (by that I mean not a deliberate change of specification rather again a tightening of process parameters) as the process matures and channel length (again due to a similar tighetning of parameters). I can see why you think the ratio will not be altered as the changing of a mask can be a major design change - however if the expected benefit of such a one off cost is improved yields then I am pretty sure it is a change they would make.
 
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