Originally posted by hitechjb1 (09-01-2003 01:07 PM)
Summary on overclocking the NF7-S rev 2.0 (with Tbred B 1700+ DLT3C and ...)
From my experience on two NF7-S rev 2.0 boards and reading results of many posts, it seems to me that there is no definite combination in terms of the following
- bios version: 10, 14, 16, 18
- L12 mod or FSB_Sense 166/200 mod
- bios setting CPU Interface enable/disable
to achieve highest FSB and memory bandwidth. It has to be tried on a board by board basis (w/ memory modules used) to achieve its max FSB potential, which averaged around 220 MHz, some lower at 210 MHz and some higher to 230 MHz, with stock chipset cooling and without chipset Vdd mod, using good 3200/3500 CAS2 memory with Vdimm at 2.8, 2.9 V if necessary.
I am going to list 6 different situations, no clear trends:
1. Some boards can go to its highest FSB with bios 14, 16, 18, without the L12 and FSB_Sense 166/200 mod (in this situation the mod may help very very little, few MHz (1-3)).
2. Some boards may need the L12 or FSB_Sense 166/200 mod to get stable higher FSB, by as much as 10-15+ MHz.
3. Some boards may need to go back to bios 10 to achieve highest stable FSB. But bios 10 is without the bios fail-safe saving feature of bios 14 or higher. One could get bios corruption w/ bios 10 and need a bios recovery kit to recover.
4. The boards may also require faster CPU above 2.2 GHz to achieve high memory efficiency around 95%.
5. Further, some boards may have stability problem and cannot run at high FSB at certain CPU multipliers (above or below are fine, strange, seeems to be some timing issues ??).
6. Some reported CPU Interface disable made a noticeable higher FSB, as much as 10-15+ MHz. But some can go to highest FSB with or without CPU Interface enabled. But CPU Interface disable has significant negative impact on memory bandwidth performance (6-8%, see below).
It seems to me that the timing of the chipset memory controller, CPU FSB interface, memory modules as a whole making the FSB overclocking very tricky and needed to be done on a case by case basis, without a definite clear recipe.
I think there is an intrinsic limit on FSB based on the combined system timing of the above mentioned components. The board's FSB overclocking would max out at certain level of memory bandwidth (MB/s), regardless of the bios versions, L12 or FSB_Sense mod, CPU Interface, dual channel or single channel, and how well the settings are tweaked and means to achieve the max FSB.
Regardless of the FSB MHz, the number to watch is the effective measured memory bandwidth and memory efficiency, which determine the overall system performance (instead of just FSB MHz). I found that
CPU interface enable (fast decode) and dual channel, integer memory efficiency ~ 95 - 96%
CPU interface disable and dual channel, integer memory efficiency ~ 88-89%
For single channel, memory efficiency would drop by 2-3% but FSB may go few MHz higher, hence single channel and dual channel is roughly a wash on effective memory bandwidth.
Main emphasis for performance should be getting CPU interface enable to work. Since the 6-8% gain of memory efficiency (as described earlier) for memory bandwidth w/ CPU interface enable would be equivalent to 12-18 MHz at the level of 200 MHz FSB. A lower FSB with higher memory efficiency may be better than a higher FSB with lower memory efficiency for both memory bandwidth performance and stability (chipset, memory controller, memory, CPU FSB interface).
Memory bandwidth (MB/s) and memory efficiency can be obtained from the latest Sandra (MAX3) memory bandwidth test, or calculated by
memory_efficiency = measured_memory_bandwidth / (16 x FSB)
