How to test for open L1s on locked CPUs

[John C.]

L1 bridges connect the 5 signal busses to pins. The tops of L3 bridges (or all of closed L3s) also connect to the 5 signal busses. So just test for continuity or low resistance between the tops of L3s to corresponding pins. If the circuits between the signal busses and their pins are closed should read no more than about 1 ohm, if open should read a lot more (as circuit between probes is made thru "other internal paths"). This might solve the mystery of recent locked Multipliers...AMD may have introduced a "disconnect" somewhere between the signal busses and their pins.

Here's the orientation of pins vs L3s...L3s left to right = 1 thru 5. Use needle or sharp pin to poke thru any film covering the L3s or their "dots".

1 = AN27
2 = AL27
3 = AN25
4 = AL25
5 = AJ27
John C.

See pics in Workarounds article to locate the pins at
http://www.beachlink.com/candjac/index.htm

[c627627]

Shouldn't the laser cuts be visible like the Thorton L2 bridge laser cut that castrates the 512 KB cache Barton into a 256 KB cache Thorton?

[John C.]

Originally posted by c627627
Shouldn't the laser cuts be visible like the Thorton L2 bridge laser cut that castrates the 512 KB cache Barton into a 256 KB cache Thorton?

Only IF "that's" how AMD chose to make the suspected "disconnect"...why can't it be somewhere else?? Someone should test.
John C.

[OC Detective]

I definitely think someone who has one of these newer cpus should do this test to verify once and for all if these cpus are locked.