Basically.
The Lower, The Better.
Not to get into definitions, but to identify terms:
CAS Latency = CAS or CL
RAS-to-CAS Delay - tRCD
RAS Precharge - tRP
RAS Pulse Width or other names - tRAS or tRC
Whenever I give timings, I try to leave out tRAS, as it generally differs for each system. Usually tRAS should be CAS + tRCD + 2 but this differs in some cases, like with nForce2 chipset (where 11 seems to be ideal).
2-2-2 (CAS-tRCD-tRP) is generally considered ideal. If the system is unstable, then you must lower the memory speed, raise the voltage, or raise the timings. Usually, the first timing to go (or which stresses the memory the most) is a tRCD set to 2. Alot of memory cannot handle this, especially with less then 3V. Raising the tRCD to 3 also has the most significant single timing step effect on your memory performance.
The performance hit by raising timings decreases as timings get larger (raising timings from 2-3 hurts more then 3-4, and so on). Timings are usually measured in tCK (Clock Cycles) and can be converted into ns (nanoseconds) by getting the ns-speed that the memory is running at.
Memory running at 200MHz (DDR400) has a tCK (Clock Cycle) of 5ns (use 1000 divided by memory speed - 1000/200). Timings of 2-2-2 (tCK) on memory running at 200MHz (DDR400) is then converted to 10-10-10 (ns). Memory running at 3-3-3 (tCK) at 250MHz (DDR500) is running at timings of 12-12-12 (3 * 1000/250) when converted to nanoseconds (ns).
For definitions of what exactly each memory timing controls, there are several descriptions online that range from overly simplistic to downright confusing.
Remembering all that stuff is kinda confusing... I just remember lower = better.
