How loose is too loose?

I have my timings at 11-2-2-2.5 right now and my FSB at 185 mem voltage at 2.9. I am getting all kinds of errors in memtest though. So back to the real question which is : how loose should I go on my timings to try to stay at 185 FSB? Any other info about my system should be in my siggy.

hmmm never seen timings that loose... usually i see 3-8-4-4

There really isn't a limit as to how loose they can be, but there is kind of one to how loose they SHOULD be. With performance in mind, I wouldn't go below 2.5-3-3-11. Actually, 2.5-2-2-11 is considered "tight" by most standards, with 2-2-2-11 being the tightest you can usually run. Dropping down to 2.5-3-3-11 should achieve much higher overclockability MHz wise.

He's written it in reverse. If he writes his timings in your format, it should be:

2.5-11-2-2

That's OK, not bad. Not very loose.

OK, sounds great. I think I'll try 2.5-3-3-11 and see were that gets me. As for the format that I wrote it in, I had no idea what is the "right" way.

hehehe ok.. i mistakenly read it lol

2.5-2-2-11 is not loose by any stretch of the imagination! They're pretty much as tight as you can get, other than 2-2-2-11.

2.5-2-2-11 is BETTER than 2-3-2-11 (the 3 being tRCD or more colloquially, RAS->CAS Delay). It is a common misconception that Cas Latency is the end-all and be-all of memory timings, but it's been shown quite conclusively that RAS->CAS delay impacts performance more.

As for order, *most* people write it in terms of:

CAS LATENCY - tRCD - THE OTHER ONE - tRAS, although sometimes tRCD and "the other one" are interchanged. lol.

yes, i agree.