What Makes a PIII faster than a Celeron?

[Endeavor]

in the blue corner...
Intel's PIII 800@100 FSB
in the red corner...
Intel's Celeron 800@100 FSB
what makes the PIII faster?
is it the cache?

[Placid]

256k cache.

[dozier768]

well in the case of the amd and the duron it is the cache, im not into intels anymore so i really dont know but that is what i would assume

[Richard]

Cold hard cache baby. :)

The celeron is a crippled P!!!. Not only is half the cache shut down, but there are increased latencies to further weaken it. Pretty smart if you think about it. Why design a whole different chip?

Endeavor (Jul 29, 2001 07:08 p.m.):
in the blue corner...
Intel's PIII 800@100 FSB
in the red corner...
Intel's Celeron 800@100 FSB
what makes the PIII faster?
is it the cache?

[Endeavor]

so if i were to magically put more cache on my celeron 700 it would ALMOST be as nice as a regular PIII?

[alex]

I don't think you can add more cache to a processor (unless it is on a little board that you plug into the mobo - i think older models had this !)

[Shadow ÒÓ]

not just cache. There's a whole slew of instructions the P III has that the Celery doesn't . They're not nearly as similiar as you might think.

[*spazzed*]

The celeron doesn't have SSE technology. The Plll does though, and the P4 has SSE2 technology.

[gdog]

Not just cache, but the set associativity of the cache also.

[Endeavor]

what do you mean by that?

[markedmundb]

*spazzed* (Jul 30, 2001 10:21 a.m.):
The celeron doesn't have SSE technology. The Plll does though, and the P4 has SSE2 technology.

The Celeron 2 (533a, 566 upwards) do!

[*spazzed*]

markedmundb (Jul 31, 2001 08:56 a.m.):
*spazzed* (Jul 30, 2001 10:21 a.m.):
The celeron doesn't have SSE technology. The Plll does though, and the P4 has SSE2 technology.

The Celeron 2 (533a, 566 upwards) do!

D'oh! I just found that out......sorry for false info :'(

[JigPu]

I don't know exactly what cache associations do, but I know that some are faster than others. I know of read-through, write-through, write-back, ect.

My bet for why a P3 is faster than a Celeron is the cache... I suppose that if you tried REALLY hard, you could somehow interface some cache memory directly with the die, but that would be much harder than just buying a P3. Older mobos have a chip that plugs into it forming the L2 cache. It runs at the bus speed (I think, but that dosen't make sense...), or somewhere between the CPU and BUS speed (makes more sense, but haven't heard it this way). On my P90, I have a 512K cache chip on the mobo. If I could only hook that up to a celeron :) ....

JigPu

[Mictlan]

JigPu (Jul 31, 2001 02:28 p.m.):
I don't know exactly what cache associations do, but I know that some are faster than others. I know of read-through, write-through, write-back, ect.

My bet for why a P3 is faster than a Celeron is the cache... I suppose that if you tried REALLY hard, you could somehow interface some cache memory directly with the die, but that would be much harder than just buying a P3. Older mobos have a chip that plugs into it forming the L2 cache. It runs at the bus speed (I think, but that dosen't make sense...), or somewhere between the CPU and BUS speed (makes more sense, but haven't heard it this way). On my P90, I have a 512K cache chip on the mobo. If I could only hook that up to a celeron :) ....

JigPu

Even if you manage to increase the L2 with external cache, you'll get other problems. The L2 cache of the PIII is on die, that means that is part of the core itself. That way the cache runs at the same speed than the core. Even if you use a daughter board (ala SECC package) the cache you add will be running at a different speed than the processor, and increase the latency of the data fetching instructions.

[wild_andy_c]

They are essentially the same chip, however the L2 cache of the Celeron is not only smaller than the cache of the PIII, but is also less associative, that is it is crippled further just than having less cache in order for the performance gap to be larger and to distinguish between value and prestige product. Even though less associative, the cache still runs at full chips speed.

Good old AMD do not do this with Duron and Athlon - they simply allow the Duron to be a reduced cache Athlon rather than one with broken legs.

Regards SSE, the celeron does have it - the only problem is that it cannot be seen in the same Processor ID fashion that allows P3 owners to view the special stuff on intels site. Whoever said there was no SSE is very wrong.

[Hemitboy]

I agree that the PIII is faster than the Celeron II because of cache reasons as well, and that it is because the Celeron II is essentially a PIII with half of it's cache disabled. Because the PIII has a 256K L2 8-way set associative cache, when Intel disables half of it, you get the Celeron II with a 128K 4-way set associative cache. The reduced size and set associativity DO make that much of a difference. Set associativity is essentially how parallelized the cache is. Set associative caches are a nice hybrid (a group of rows and columns) between direct mapped caches (a single 'column') and fully associative caches (a single 'row'). Rows are called 'sets' and columns are called 'ways'. What difference does that make? Well, as the set associativity increases from direct mapped (1-way) to 2-way to 4-way up to 16-way the performance increases because the cache is able to store more data without overwriting other data that has previously been stored. This becomes important when you need that information again. If the processor finds the data in the cache, called a cache hit, it is able to load the data much more quickly than if it has to load the data from the system memory. So, this translates into the fact that the PIII's cache not only has more capacity but it has a much higher hit rate, ie it has to access system memory for data far less than the Celeron II. Now figure in that for each of the times the Celeron has a cache miss, data not found in the cache, and the PIII has a cache hit, the differences will be that the Celeron II 800 is accessing the data on a 150MHz bus at the max (with overclocking) which is still nowhere near the PIII which is getting the info at the full 800MHz CPU speed...

Sorry for the length just thought some might want to know a bit more.

[kieron]

*spazzed* (Jul 30, 2001 10:21 a.m.):
The celeron doesn't have SSE technology. The Plll does though, and the P4 has SSE2 technology.

I have a PIII coppermine 800 and according to sandra 2001 it has sse2 instructions so there,