[*]The Barton is ALMOST a T-bred B with more cache. Design refinements were made, but no extra layers of silicone were added.
[*]Many of the modules (I don't recall the exact list, but things like the in the FP Scheduler, Integer Unit, Instruction Control Unit) from the Barton design are to appear in the Thorton, but not the complete L2 cache.
[*]This would make the Thorton out to be a T-bred B built with Barton grade processor modules and the original T-bred size L2 cache. So the logic portion of the chip will be mostly barton in heritage while the cache will follow from the T-bred B design. The thorton would therefore be very similar in size to the T-bred B but have some of the improved circuitry of a barton as well.
[*]To make a crippled Barton (one with some cache disabled) would be a waste of production wafer space, reduce output from the wafer, and make a Thorton just as expensive to produce as a full Barton. The microprocessor industry is all about improving yield percentages and wafer efficiency.
[*]Cache memory on the die is probably the least likely portion to fail in the production process, so the likelyhood of flawed cache chips is very small...too small to market the mistakes as another core.