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please help me understand a64 arcitechture....

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MorGoth

Member
Joined
Mar 18, 2004
Location
CT
ok....i'm quite confused as to how a64 architechture works and i was hoping some more experienced/knoweldgeable users could please help me understand it...this is what i know so far....

1. there is an intergraterd memory controller in the chip that operates at pc3200 speeds of 400mhz.

2. there is a separate HT bus that operates at up to 1600mhz (depending on the motherboard chipset) which connects the I/O devices and stuff like that...

ok, with that being said (oh yeah, if any of the above is wrong please correct me), does your RAM come into play at all when you are overclocking? if the memory controller is already in the chip....how does your RAM affect your oc?...(that may be a stupid question...but thats why i'm asking it...) can someone please explain to me how this stuff really works....and how you would oc it?....i am going to be getting one of these when summer starts and I would really like to know how it works....Thank you very much

MorGoth
 
the memory controller is in the cpu, it runs at the full speed of the cpu and your ram runs at whatever speed you set it to in bios. while the underlying technology is different than the athlon xp, it overclocks about the same in bios. you have a multi setting (only unlocked downward on all but fx's) a fsb setting (200mhz stock) and ram speed settings. i have an a64 3000+ running at 220mhz fsb and 10 multiplier w/ ram 1-1 at 220. all in all, if you can work through the bios of your current board you would do fine overclocking my current a64/ msi k8t neo combo
 
What about memory dividers? They are set seperately right? What if I wanna run my CPU at like 2.4Ghz, 240FSB, with 220Mhz ram?

Thanks
 
hkp0lice said:
What about memory dividers? They are set seperately right? What if I wanna run my CPU at like 2.4Ghz, 240FSB, with 220Mhz ram?

Thanks

The Athlon64--as well as any CPU that has an on chip memory controller--does not have a front side bus per se. It's integrated into the chip and runs at the full speed of the processor.

Separate and distinct from the DDR memory bus you have HyperTransport perhipheral bus links to the PCI bus bridge(s). This is the only "front side bus" that the CPU has, and even then it's more of a backplane, connecting the I/O device bus adapters to the processor.
 
I get it, but I just had to make sure of somethin. Theres 2 multiplyers right? 1 for the HT x CPU = CPU speed, and another for the memory speed = CPU / X. So X can be selected on every motherboard?
 
hitechjb1 said:
Differences between XP FSB and the A64 buses (separate memory bus and HyperTransport bus)

For XP, memory data, video card data, PCI data (hard disk, optical drives, networking, ...), serial links (USB, firewires, ...), slower peripheral (keyboard, mouse, ...), everything are going through the FSB to/from the CPU.

...

The traffic that are crucial to system performance such as memory data, video card data, hard disk data (file I/O, paging) have to compete with other in the FSB, result in bottleneck and system bus conflct.


For the A64 CPU, the memory traffic and the traffic for the rest of the devices mentioned above are separated at the CPU rather than at the chipset (NB). This is the key difference in system bus architecture between the old XP and the new A64, and has an important advantage of system performance for the A64.

- Memory is communicating directly via a separate memory bus to the processor's on-chip dual channel memory controller with 128-bit data path (for 939/940) and on-chip single channel memory controller with 64-bit data path (for 754).
In an other post, the effective bandwidth for the 128-bit dual channel is estimated around 90% of max bandwidth, which is higher than the 75% number of P4 dual channel QDR.

- The rest of the subsystems such as video, hard drives (IDE, SATA, RAID), optical drives, networking, serial links, multi-CPU communication (for multi-processor board), ..., are comunicating to/from the CPU via the HyperTransport bus to the chipset and various bridges down stream.

...
(Skip details about HyperTransport, refer to link for details.)

Summary:

Due to the separation of memory bus and HyperTransport (system) bus for all other devices in A64,
- the effective latency between the CPU (after L2 miss) and the memory (L3) is reduced
- the effective bandwidth of the A64 memory bus (128-bit in 939) to/from the CPU is alone higher than the highest effective P4 memory bandwidth, and twice that of XP
- the max bandwidth of the HyperTransport bus (for all other devices) to/from the CPU is alone comparable to P4 system bus, twice that of XP

The max combined bandwidth of memory bus (in 939) and HyperTransport in an A64 system is more than twice the sytem bus (FSB) of a P4 system and four times the system bus (FSB) of an XP system.


Estimation and importance of 939 platform memory bandwidth (page 19)

Differences between the XP FSB and the A64 buses (separate memory bus and HyperTransport bus) (page 19)
 
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