wireboy
08-22-01, 09:14 PM
Found a book at the used bookstore that had some intresting information in it:
"Circuits, Interconnections, and Packaging for VLSI" by H.B. Bakoglu ISBN 0-201-06008-6
which mentions high-performance chip cooling solutions. Here's the relevant part in chapter 3 page 122:
"
A structure that brings the chips in direct contact with the coolant fluid is illustrated in fig. 3.34. Here a jet of chilled water hits directly on the backside of the die, and a flexible bellow structure provides conformance to the chip surface. Using this concept, a thermal resistance of 2 to 3 deg. C/W for 7.5 X 7.5 mm chips has been achieved [3.53]. As a result a chip can dissipate 75W of power and maintain a junction temperature only 25 deg C above the cooling water temperature.
"
I've seen experiments with this technique mentioned on the web, and the results seemed to be around .1 deg C/W. I tried this myself with a duron dissipating 54 watts(calc'd with Radiate), and got around .4 degC/W with DI water flowing at 80GPH (calibrated thermocouples on case underside & water inlet). Not too impressive.
Bakoglu then goes on to mention in the next paragraph:
"
The efficiency of the heat transfer can be tremendously improved by fabricating the heat sink directly on the semiconductor wafer itself (fig 3.35). This eliminates the interface between the die and the heat spreader and improves the thermal resistance of the package. In a study conducted at Stanford University, microscopic channels 50um wide and 400um deep were mechanically cut on the backside of a silicon wafer and were closed by a cover plate to confine a fluid flow forced through them [3.49]-[3.50]. These microscopic laminar flow heat exchangers are shown to provide heat removal rates better than 0.1 W/degC-cm^2. Using this method, heat fluxes as large as 1kW/cm^2 can be removed while keeping the junction and ambient temperature differential below 100degC. In an independent study conducted at Motorola, similar microchannels were mechanically cut on a 3.8x3.8 cm silicon substrate, and by forcing water flows of 12 and 63cm^3/s, thermal resistances of 0.03 and 0.02 degC/W were obtained [3.43]. This corresponds to heat removal rates of 2.4 and 3.6 W/degC-cm^2. When air was used as a coolant, thermal resistances of 1.0-0.7 degC/W were obtained, which correspond to a heat removal rate of 0.07-0.1 W/degC-cm^2.
These microchannels can be fabricated on the chips themselves, or by using a silicon-on-silicon hybrid technology the chips can be mounted on substrates witht eh micro cooling channels. The existence of an interface between the chip and the substrate reduces the efficiency of the heat removal mechanism in a silicon-on-silicon hybrid, but since the substrate can remove so much heat, the overall result most likely will be superior to other alternatives. Long-term reliability of this cooling scheme needs to be carefully studied. A source of concern is the possible clogging of some of the microchannels by accumulation of the particles in the cooling water. This may give rise to local hot spots, which will accelerate a number of device and packaging failure mechanisims.
"
Well, in the case of the duron that would be .07 degC/W, which seems pretty good to me! I'm tempted to try this out on a low-end duron, but I'm wondering how far into the substrate I can saw. I really don't have too much clue when it comes to how the duron (or any other CPU) is made, but I have access to a low-volume chip manufacturing facility, and they might let me use their junker chip dicing saw to cut the microchannels. Is it worth a few hours and a $35 duron to try this type of cooling?
References from above paragraphs (web searches were somewhat productive):
[3.49]
D.B. Tuckerman and F. Pease, "High performance heat sinking for VLSI", IEEE Electron Device Letters, vol. EDL-2, no.5, pp.126-129, May 1981
paper ref'd at bottom of this webpage:http://www.cise.ufl.edu/~mpf/week4.html
[3.50]
D.B. Tuckerman, "Heat-transfer microstructures for integrated circuits", Ph.D. dissertation, Stanford University, 1984
[3.43]
M. Mahalingam, "Thermal management in semiconductor device packaging", Proceedings of the IEEE, vol. 73, no. 9, pp. 1396-1404, Sept. 1984
[3.53]
R.J. Petschauer, "Evolution of high performance computer packaging", Professional Program Session Record of WESCON/85, session 7, Nov. 1985
There's another book by Bakoglu available online:
http://books.nap.edu/books/030904233X/html/61.html#pagetop
check the 4th paragraph for a reference to desktop systems (in 1990!).
"Circuits, Interconnections, and Packaging for VLSI" by H.B. Bakoglu ISBN 0-201-06008-6
which mentions high-performance chip cooling solutions. Here's the relevant part in chapter 3 page 122:
"
A structure that brings the chips in direct contact with the coolant fluid is illustrated in fig. 3.34. Here a jet of chilled water hits directly on the backside of the die, and a flexible bellow structure provides conformance to the chip surface. Using this concept, a thermal resistance of 2 to 3 deg. C/W for 7.5 X 7.5 mm chips has been achieved [3.53]. As a result a chip can dissipate 75W of power and maintain a junction temperature only 25 deg C above the cooling water temperature.
"
I've seen experiments with this technique mentioned on the web, and the results seemed to be around .1 deg C/W. I tried this myself with a duron dissipating 54 watts(calc'd with Radiate), and got around .4 degC/W with DI water flowing at 80GPH (calibrated thermocouples on case underside & water inlet). Not too impressive.
Bakoglu then goes on to mention in the next paragraph:
"
The efficiency of the heat transfer can be tremendously improved by fabricating the heat sink directly on the semiconductor wafer itself (fig 3.35). This eliminates the interface between the die and the heat spreader and improves the thermal resistance of the package. In a study conducted at Stanford University, microscopic channels 50um wide and 400um deep were mechanically cut on the backside of a silicon wafer and were closed by a cover plate to confine a fluid flow forced through them [3.49]-[3.50]. These microscopic laminar flow heat exchangers are shown to provide heat removal rates better than 0.1 W/degC-cm^2. Using this method, heat fluxes as large as 1kW/cm^2 can be removed while keeping the junction and ambient temperature differential below 100degC. In an independent study conducted at Motorola, similar microchannels were mechanically cut on a 3.8x3.8 cm silicon substrate, and by forcing water flows of 12 and 63cm^3/s, thermal resistances of 0.03 and 0.02 degC/W were obtained [3.43]. This corresponds to heat removal rates of 2.4 and 3.6 W/degC-cm^2. When air was used as a coolant, thermal resistances of 1.0-0.7 degC/W were obtained, which correspond to a heat removal rate of 0.07-0.1 W/degC-cm^2.
These microchannels can be fabricated on the chips themselves, or by using a silicon-on-silicon hybrid technology the chips can be mounted on substrates witht eh micro cooling channels. The existence of an interface between the chip and the substrate reduces the efficiency of the heat removal mechanism in a silicon-on-silicon hybrid, but since the substrate can remove so much heat, the overall result most likely will be superior to other alternatives. Long-term reliability of this cooling scheme needs to be carefully studied. A source of concern is the possible clogging of some of the microchannels by accumulation of the particles in the cooling water. This may give rise to local hot spots, which will accelerate a number of device and packaging failure mechanisims.
"
Well, in the case of the duron that would be .07 degC/W, which seems pretty good to me! I'm tempted to try this out on a low-end duron, but I'm wondering how far into the substrate I can saw. I really don't have too much clue when it comes to how the duron (or any other CPU) is made, but I have access to a low-volume chip manufacturing facility, and they might let me use their junker chip dicing saw to cut the microchannels. Is it worth a few hours and a $35 duron to try this type of cooling?
References from above paragraphs (web searches were somewhat productive):
[3.49]
D.B. Tuckerman and F. Pease, "High performance heat sinking for VLSI", IEEE Electron Device Letters, vol. EDL-2, no.5, pp.126-129, May 1981
paper ref'd at bottom of this webpage:http://www.cise.ufl.edu/~mpf/week4.html
[3.50]
D.B. Tuckerman, "Heat-transfer microstructures for integrated circuits", Ph.D. dissertation, Stanford University, 1984
[3.43]
M. Mahalingam, "Thermal management in semiconductor device packaging", Proceedings of the IEEE, vol. 73, no. 9, pp. 1396-1404, Sept. 1984
[3.53]
R.J. Petschauer, "Evolution of high performance computer packaging", Professional Program Session Record of WESCON/85, session 7, Nov. 1985
There's another book by Bakoglu available online:
http://books.nap.edu/books/030904233X/html/61.html#pagetop
check the 4th paragraph for a reference to desktop systems (in 1990!).