Both DRAM and EDO DRAM have worked quite well at bus speeds of 66MHz and less. Many 486 class computers run with 33MHz buses while newer Pentiums use a 66MHz bus. However, the newest CPU's are being designed for bus speeds of 100MHz and up. Motherboards with these speeds will be appearing in quantity before mid-1998. Although, some high-end machines from Compaq, Dell, and Micron are already showing up with these faster buses and the Pentium II CPU. Neither DRAM nor EDO DRAM can work with these bus speeds above 66MHz. This is partly due to the asynchronous nature of the chips. They are independent of the system clock and move data only on command from the CPU. This results in wait states which slow data transmission. The solution to this problem is the Synchronous DRAM chip. This chip has a clock input which allows the system clock to coordinate memory functions. The SDRAM chip then cycles at a much faster speed because it is functioning in concert with the CPU. For example, in a chip with a 50 nanosecond access time, the second cycle time is 30ns for FPM DRAM, 20ns for EDO DRAM and 10ns for SDRAM. The ability to provide data in half the time is part of the advantage of the synchronous chips.
