- Joined
- Dec 21, 2004
- Location
- los angeles
Just reread the xbit ddr2 article
First article is irrelevant to any AMD user especially A64 with integrated memory controller.
Seond cost and cost/performance is not cosidered
Third IMHO announcing DDR 466 (233 mhz) and DDR 533 (266MHZ) support with appropriate dividers for PCI and HT would go a long way in prolonging current architecture- and would be essentially 0$ chipset cost delta.
Such memory is already available at various latencies/ prices
fourth it s the speed of the L1-L2 cache which is MOST important, the memory speed is not nearly as important (for most applications)
fifth $$$ are usually best spent on faster l1-l2 cache
sixth larger l2 cache is very application dependent for single task, more important for multi tasking but multi-tasking benchmarks are rare
(This is the reason for 1 mb caches available for server chips)
seventh
larger l2 cache will be more important with dual chip processor modules
eighth more inexpensive memory can be more important than faster memory or lower latency memory for the same $$$
ninth
ECC memory (socket 940) can be mission critical even with the added wait state, if required
for those of us individuals or corporations on a bucget benchmarks which not price adjusted are just a start- there are always trade-offs
wyrmrider
good article ED
First article is irrelevant to any AMD user especially A64 with integrated memory controller.
Seond cost and cost/performance is not cosidered
Third IMHO announcing DDR 466 (233 mhz) and DDR 533 (266MHZ) support with appropriate dividers for PCI and HT would go a long way in prolonging current architecture- and would be essentially 0$ chipset cost delta.
Such memory is already available at various latencies/ prices
fourth it s the speed of the L1-L2 cache which is MOST important, the memory speed is not nearly as important (for most applications)
fifth $$$ are usually best spent on faster l1-l2 cache
sixth larger l2 cache is very application dependent for single task, more important for multi tasking but multi-tasking benchmarks are rare
(This is the reason for 1 mb caches available for server chips)
seventh
larger l2 cache will be more important with dual chip processor modules
eighth more inexpensive memory can be more important than faster memory or lower latency memory for the same $$$
ninth
ECC memory (socket 940) can be mission critical even with the added wait state, if required
for those of us individuals or corporations on a bucget benchmarks which not price adjusted are just a start- there are always trade-offs
wyrmrider
good article ED
