- Joined
- Apr 9, 2001
Well, Tras (the "5" or "6" timing, here, also called RAS pulse width (ROW ACCESS STROBE pulse width), by simple logic, -has- to be, at lowest, cas latency time + cas to ras delay, since Tras, in laymans terms is the latency of how long a bank is actually available for reading (like opening a book)--(not how long it takes data to be retrieved)
But there has to be at least 2 more clock delays added, because with DDR, eight consecutive quadwords are output (by the controller) on every access. (with regular SDRAM, 4 consecutive quadwords), so while EDO Ram has single word data transfers (thus 2-2-2-4 would be just fine, if such a timing were available back then), SDRAM naturally needs 2-2-2-5 with its 4 quadwords. And since DDR is double data rate (and thus 8 quadwords instead of 4), you need an extra delay=2-2-2-6 timings, under ideal situations.
This information was taken from mushkin's webpage.
They claim: running RAM at 2-2-2-5 increases the chances of a truncated transfer (the bank is suddenly closed), that needs to be repeated--thus, a performance penalty is applied (and there is a risk of data corruption as well, if the data is written to a hard disk cache at system shutdown, before the transfer is repeated).
A similar thing for running at 3-3-3-6 (obviously, this is actually worse than 2-2-2-5)--you should run at 3-3-3-8.
But this still begs the question: what about 3-4-4-8? (since 3-4-4-9, apparently ideal, isn't attainable, at least not on any intel chipset).
But there has to be at least 2 more clock delays added, because with DDR, eight consecutive quadwords are output (by the controller) on every access. (with regular SDRAM, 4 consecutive quadwords), so while EDO Ram has single word data transfers (thus 2-2-2-4 would be just fine, if such a timing were available back then), SDRAM naturally needs 2-2-2-5 with its 4 quadwords. And since DDR is double data rate (and thus 8 quadwords instead of 4), you need an extra delay=2-2-2-6 timings, under ideal situations.
This information was taken from mushkin's webpage.
They claim: running RAM at 2-2-2-5 increases the chances of a truncated transfer (the bank is suddenly closed), that needs to be repeated--thus, a performance penalty is applied (and there is a risk of data corruption as well, if the data is written to a hard disk cache at system shutdown, before the transfer is repeated).
A similar thing for running at 3-3-3-6 (obviously, this is actually worse than 2-2-2-5)--you should run at 3-3-3-8.
But this still begs the question: what about 3-4-4-8? (since 3-4-4-9, apparently ideal, isn't attainable, at least not on any intel chipset).
2-2-2-5 is "closing" the bank before the destructive read operation is finished (and contents are written back), so the memory controller has to keep retrying those operations.
