Why do chip manufacturers use such small dies

Couldn't manufacturers use bigger dies on CPU/GPUs? More room to work with, so they could add more transistors and more cache. Yeah more heat and more cost, but is it really THAT significant to not do it?

Please comment.

I think its mainly cost, you would need bigger heatsinks, becasue of the larger surface area, and the larger heat output, and the what not. And I don't think the jump in cost would be equal to the jump in performance

dicecca112 said:

I think its mainly cost, you would need bigger heatsinks, becasue of the larger surface area, and the larger heat output, and the what not. And I don't think the jump in cost would be equal to the jump in performance

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It is a cost issue, but not one associated with heatsinks or such. The smaller the die the more chips you can fit on a silicon wafer. If a cpu manufactuer can fit 200 cpu's on a 12" wafer using the 90nm process and 300 cpu's using the 65mn process it means they get 50% more chips without processing more wafers.

Couldn't manufacturers use bigger dies on CPU/GPUs? More room to work with, so they could add more transistors and more cache. Yeah more heat and more cost, but is it really THAT significant to not do it?

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Lowering the die process DOES give them more room to work with. The smaller everything, is the more they can fit on a single die. There's also more to a die than pure room...extra cache and extra transistors cost a whole lot, and extra cache increases the chances of part of the cache being unusable.

Agreed. The chunks of silicon they cut wafers from can cost 1/4 mil, and the more processors they get from that slab, the easier it is to absorb that cost.

Die size effects heat issues in the opposite direction. A larger die has more surface area to transfer heat away, a smaller die has less. The smaller the die size, the better the heatsinks must be to remove the same wattage.
Smaller dies can have an advantage in using less wattage because of shorter conductors within it's circuitry, but the closer the etched components are together, the more they start leaking voltage and use more than they "should" to do the same job. Catch 22.

Personally I'd like to see them etch a processor out on a single layer of silicon deposited on a copper sheet. Put it on the backside of the mobo and they can be as large as they want, and the buses they feed can have direct lines into the cpu without passing around the mobo so much, and without an NB/SB at all.
Cool, Efficient, Cheap. But what do I know?

A lot of the silicon that the chips are produced on is wasted anyway. Most fabs use wafers that range in thickness form 35mil to 50mil thick. The thicker the wafer the stronger and more stable it will be during the processing. Also most fabs process the chips with all the circiuitry on one side only. After the processing is completed the fabs will lap the back side of the wafer (unprocessed side) untill the the wafer is reduced in thickness, sometimes down to 10mil or so.

Now I work for a semiconductor manufacture and we start out with 6 to 12mil wafers. The reason our wafers start out thin is our chips are patterned on both sides which allows a smaller chip than you would get if it was processed on 1 side only.

I'm surprised this has yet to be mentioned. One of the main things about small cores is TIME, You can't go fast when the electrons have far to go. So, they go smaller and smaller to get faster and faster, not to mention it also reduces the natural capacitance of any conductor which is one of the bigger speed limits.
basically:
small size:
pros:
less capacitance in the traces
less silicon needed
less time for electricity to get from point "a" to point "b"
cons:
more resistance so more heat
less area to spread the heat out

couldn't they get bigger dies but the same sized process (like instead of a 1.5x1.5cm die with a 90nm process, couldn't they have like a 2x2cm die with a 90nm process)?

edit: Like, couldn't they have like, two 90mm wafers side by side? yeah, its gonna be damned expensive, but wouldn't it give good performance? Or not enough to justify the price (going from 250k to 500k in cost, rough estimate)

I've been wondering the same question for years...for things like cell phones...CPUs...everything. Seems like people/buisinesses are so concerned w/ stuff being SOOOO DAMN TINY and packing power, instead of it being the same size as older stuff but having 2x the power inside...never really made alot of sense to me lol, im just wondering when people will start losing their cell phones cause of htem being too damn small.

If the die is smaller, then a defect in the wafer will affect a smaller percentage of the chips.

Like, couldn't they have like, two 90mm wafers side by side?

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It's called dual core.

Smaller dies can have an advantage in using less wattage because of shorter conductors within it's circuitry, but the closer the etched components are together, the more they start leaking voltage and use more than they "should" to do the same job.

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Which is why AMD is using SOI technology.

couldn't they get bigger dies but the same sized process (like instead of a 1.5x1.5cm die with a 90nm process, couldn't they have like a 2x2cm die with a 90nm process)?

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Why would they? They save silicon this way, and they can make it that small. They can make the more powerful processors smaller too. Remember that all of these processors do fine in terms of heat when they're run at stock, and that's all the manufacturers care about. They're not going to start changing die sizes to cater to overclockers' cooling needs.

As has been said before, the biggest motivator for making things smaller and smaller is to increase profits. If you can fit 100 dies on a wafer at 130nm, then you can (theoretically) fit 140 at 90nm. You can then go and sell these 40 extra processors at the same price, or lower the prices a bit and still make money from them.

As for doubling die size for doubling performance, the only real way to do this is to go dual core. Doubling the cache helps minimally above 512KB, and doubling the number of functioning units can become a pain in the butt for the chip designers. Also, making a single core physically larger decreses it's maximum speed (in GHz) like sunrunner20 said because of the effect time begins to play. Dual core is a fairly elegant solution to these problems, even if it also dosen't achive 2x the speed in average circumstances of today. The problem of course is that to maintain the same profit for a dual core chip, one must charge 2x as much for it which will decrease demand considerably.

JigPu

Smaller dies will acctually increase the level of non functional CPUs, so wafer flaws are kinda moot, along with the fact that you might have several cpus killled by a flaw instead of a single one. I stick with the fact that they are smaller becuase we are pussing the limits on how far electrisity will go in the time allowed...

Dell_Axim said:

It's called dual core.

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Dual core has nothing to do with two wafers. It has two cores on the same die. This die is cut from a wafer, just like any other die.

sunrunner20 said:

I'm surprised this has yet to be mentioned. One of the main things about small cores is TIME, You can't go fast when the electrons have far to go.

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While the speed of electrons in moving current is fairly low, current moves very fast. If you're worried about time, your worried about the time it takes current to move, which is substantially less time than it takes the electrons to move.

Without going into quantum physics, in which I have little experience:

Electricity "travels" at the speed of light. For a 3.0 GHz processor, the signal can only travel 10 centimeters in one clock cycle. If it needs to get across the processor twice for some reason, the latency will be greatly reduced if the core is only 1 cm wide as opposed to 4 cm wide.

Restorer said:

Without going into quantum physics, in which I have little experience:

Electricity "travels" at the speed of light. For a 3.0 GHz processor, the signal can only travel 10 centimeters in one clock cycle. If it needs to get across the processor twice for some reason, the latency will be greatly reduced if the core is only 1 cm wide as opposed to 4 cm wide.

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I was just trying to make the point that while current moves very fast, the electrons themselves move rather slowly. It is not, as stated by a previous poster, the time it takes electrons to move that is a concern, but the time it takes current to flow.

I'd also like to make the point that transistor count has been increasing. Chips are getting more complex and powerful as they get physically smaller.

Gnufsh said:

I was just trying to make the point that while current moves very fast, the electrons themselves move rather slowly. It is not, as stated by a previous poster, the time it takes electrons to move that is a concern, but the time it takes current to flow.

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Right, I was not disputing the correctness or relevancy of your post, simply expanding on it.

Gnufsh said:

I'd also like to make the point that transistor count has been increasing. Chips are getting more complex and powerful as they get physically smaller.

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Indeed. Also, processor design on the higher levels is getting increasingly complex. Compare the logic design of, say, the 680x0 processor to the new Cells. Small individual dies are advantageous in that case because stuffing 8 of them into a processor with some other silicon while keeping the size down is crucial.

WOW. I have the answer. For the first time, I can actually use my Electrical Engineering degree from UCD to help.

Several reasons have been mentioned already. Its cheaper for companies to get dies out of a single wafer. But the fundamental limit is about 1cm or so, because:

First, silicon wafers are about 99.9999999% pure. What that means is that there are essentially no unwanted impurities, such as specs of dust or atoms of oxygen, atoms of hyrdogen, any other impure metals. Yet, even with that amount of purity, if you imagine a wafer with billiions of atoms, many impurities will be present no matter what. And these impurities, no matter how small, can be labeled as "catasrophic defects" which will render the processor useless.

So now, for our purposes, imagine a square wafer with 3 "catastropic defects" randomly placed on the wafer. If you cut the square wafer down the middle to create two processors, then most likely, each of the two processors/wafers will not work: YIELD = 0%. Now, if cut the square in fours, then it could be only 1 out of the four processors will work: YIELD = 25%. Again, now cut it into 9 pieces. Your yield now can be 6/9, 66%. Cut it into 16 pieces, yield is now 13/16..and you get the point.

Imagine this on a larger scale. These days, the yield is something like 50 some percent, which is considered good, i think. The smaller dies you make, the more yield you get and the more money you make at a lower cost.

Someone then once did the statistics and played around w/ math, and noticed that if you build procs bigger than 1cm by 1cm, the yield that you can get will not be worth the cost to build the processors, hire the engineers, build the billion dollar manufacturing plants.

Hope this helps.

Which effectively comes back to cost. The lower the yields the higher the overall cost of the chip.