- Joined
- Jul 15, 2004
- Location
- Loma Linda, CA
A little background in the AMD CPUs section: http://www.ocforums.com/showthread.php?t=405703
Here's where I'm at:
290x9, 1.46v, 1:1 primed for 15 hours before I stopped it to tweak some more. I have reached DDR600 by loosening some timings, it will do a 1M SuperPi, bt not 32M. I lowered CPU multi to 8 so I can tweak just the memory.
HT/FSB: 300
HT multi: 2.5x
CPU multi: 8x (2400mhz)
CPU volt: (1.325 + 123%) 1.46 (read from MBM5 / ITE SmartGuardian)
Vdd: 2.9v
LDT Volt: 1.5
Chipset: 1.8
DRAM Timings:
1T
Tcl: 2.5
Trcd: 4
Tras: 6
Trp: 3
Trc: 9
Trfc: 14
Trrd: 2
Twr: 2
Twrt: 2
Trwt: 2
Tref: 3072
Twcl: 1
Banke int: Enable
Skew control: 255 +
Drive Strength: 7
Data strength: 1
Max. Async: 8ns
Read Preamble: 5ns
Idle Cycle: 256
Dyn. Counter: Enable
R/W BYpass: 16x
Bypass Max: 7x
32Bit Gran.: Disable
Setting data strength from 2 to 1 helped me go from 290 to 300.
I tried setting Trp from 3 to 4 and Tras from 6 to 10, but gained no stability.
What else should I try? Anything I could do to get Trcd 3 back? Once I get the memory stable, I'll see what my Venice has left in it.
Here's where I'm at:
290x9, 1.46v, 1:1 primed for 15 hours before I stopped it to tweak some more. I have reached DDR600 by loosening some timings, it will do a 1M SuperPi, bt not 32M. I lowered CPU multi to 8 so I can tweak just the memory.
HT/FSB: 300
HT multi: 2.5x
CPU multi: 8x (2400mhz)
CPU volt: (1.325 + 123%) 1.46 (read from MBM5 / ITE SmartGuardian)
Vdd: 2.9v
LDT Volt: 1.5
Chipset: 1.8
DRAM Timings:
1T
Tcl: 2.5
Trcd: 4
Tras: 6
Trp: 3
Trc: 9
Trfc: 14
Trrd: 2
Twr: 2
Twrt: 2
Trwt: 2
Tref: 3072
Twcl: 1
Banke int: Enable
Skew control: 255 +
Drive Strength: 7
Data strength: 1
Max. Async: 8ns
Read Preamble: 5ns
Idle Cycle: 256
Dyn. Counter: Enable
R/W BYpass: 16x
Bypass Max: 7x
32Bit Gran.: Disable
Setting data strength from 2 to 1 helped me go from 290 to 300.
I tried setting Trp from 3 to 4 and Tras from 6 to 10, but gained no stability.
What else should I try? Anything I could do to get Trcd 3 back? Once I get the memory stable, I'll see what my Venice has left in it.