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memory settings on the ak31
- Thread starter amok
- Start date
- Joined
- Dec 18, 2000
My Memory Settings @ 154 MHz - AK31S907 Performance BIOS
DRAM Clock = Host Clock
DRAM Timing = Manual
SDRAM Cycle Length = 2
Bank Interleave = 4 bank
DRAM Command Rate = 2T
Precharge to Active = 2T
Active to Precharge = 5T
Active to CMD = 2T
DRAM Clock
This must be set to Host Clock for the maximum memory speed. If set to SPD, the the speed is set in accordance with information read from the Crucial DIMM itself. So you want to set this to Host Clock.
DRAM Timing
This must be set to Manual in order for the SDRAM Cycle Length, DRAM Command Rate and Bank Interleave Mode to become active. If set to SPD, the timing is set conservatively in accordance with information read from the Crucial DIMM itself. So you want to set this to Manual.
DRAM Cycle Length
The DRAM Cycle Length combines setting of CAS latency, tRCD (Active to CMD), tRP (Precharge to Active) and tRAS (Active to Precharge) to a single combo with only two options. According to WPCREDIT the settings are either 2-2-2-5 (set at 2) or 2.5-3-3-6 (set at 2.5). On most AK31 BIOSes, you only have this setting and not the Precharge to Active, Active to Precharge, and Active to CMD settings. The AK31S907 Performance BIOS provides the extra settings so you can fully tweak the memory performance and then this setting only involves CAS latency.
Bank Interleave
Bank interleave can be set manually, depending on the capabilities of the DRAM chips. The 4 Bank setting seems to work well with Crucial DIMMs.
DRAM Command Rate
Sets the command latency for the type of DDR memory used. The standard mode is a latency of two cycles, meaning that the command latched onto the DRAM on the rising edge of the second clock. This is appropriate for Registered DDR and is a safe setting for unbuffered (non-registered DIMMs) DDR. For unbuffered DDR, the KT266 offers the option to reduce the command latency to 1 cycle, meaning that the command is latched on the next rising edge of the clock signal. This usually won’t work right on the AK31 Rev 2 but seems to work OK on the KT266A Rev 3.1. So keep it at 2.
Precharge to Active - Optional
tRP – Set at 2 for best performance.
Active to Precharge - Optional
tRAS – Set at 5 for best performance. Since tRAS violations can cause severe data corruption, set this at 6 if you have any problems. It works fine in my system set at 5 with the FSB at 154 MHz though.
Active to CMD - Optional
tRCD – Set at 2 for best performance.
DRAM Clock = Host Clock
DRAM Timing = Manual
SDRAM Cycle Length = 2
Bank Interleave = 4 bank
DRAM Command Rate = 2T
Precharge to Active = 2T
Active to Precharge = 5T
Active to CMD = 2T
DRAM Clock
This must be set to Host Clock for the maximum memory speed. If set to SPD, the the speed is set in accordance with information read from the Crucial DIMM itself. So you want to set this to Host Clock.
DRAM Timing
This must be set to Manual in order for the SDRAM Cycle Length, DRAM Command Rate and Bank Interleave Mode to become active. If set to SPD, the timing is set conservatively in accordance with information read from the Crucial DIMM itself. So you want to set this to Manual.
DRAM Cycle Length
The DRAM Cycle Length combines setting of CAS latency, tRCD (Active to CMD), tRP (Precharge to Active) and tRAS (Active to Precharge) to a single combo with only two options. According to WPCREDIT the settings are either 2-2-2-5 (set at 2) or 2.5-3-3-6 (set at 2.5). On most AK31 BIOSes, you only have this setting and not the Precharge to Active, Active to Precharge, and Active to CMD settings. The AK31S907 Performance BIOS provides the extra settings so you can fully tweak the memory performance and then this setting only involves CAS latency.
Bank Interleave
Bank interleave can be set manually, depending on the capabilities of the DRAM chips. The 4 Bank setting seems to work well with Crucial DIMMs.
DRAM Command Rate
Sets the command latency for the type of DDR memory used. The standard mode is a latency of two cycles, meaning that the command latched onto the DRAM on the rising edge of the second clock. This is appropriate for Registered DDR and is a safe setting for unbuffered (non-registered DIMMs) DDR. For unbuffered DDR, the KT266 offers the option to reduce the command latency to 1 cycle, meaning that the command is latched on the next rising edge of the clock signal. This usually won’t work right on the AK31 Rev 2 but seems to work OK on the KT266A Rev 3.1. So keep it at 2.
Precharge to Active - Optional
tRP – Set at 2 for best performance.
Active to Precharge - Optional
tRAS – Set at 5 for best performance. Since tRAS violations can cause severe data corruption, set this at 6 if you have any problems. It works fine in my system set at 5 with the FSB at 154 MHz though.
Active to CMD - Optional
tRCD – Set at 2 for best performance.
- Joined
- Dec 18, 2000
Well, I guess you need to read a little more thoroughly.
To get those settings you need to flash the AK31S907 Performance BIOS, which I can send to you if you're interested. I've been running that BIOS for more than 2 months and it is very fast and stable.
To get those settings you need to flash the AK31S907 Performance BIOS, which I can send to you if you're interested. I've been running that BIOS for more than 2 months and it is very fast and stable.
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