Tras timing

I have a question about Tras timing. DFI-Street Memory guide for upper end memory says to take CAS + tRCD + (0.5 or 1.0) = tRAS. My CAS is 2.5 and tRCD is 3 so that would be about 6-6.5 (7 rounding up) with lower = faster. Experimented with my memory the other day and found I could take my tRAS all the way to 0 and memtest would not make a single error. Even had it running Stress Prime to stress RAM for couple hours. It appeared 0 was slightly slower than 6 in Super Pi but 1 was the sweet spot and gave me the fastest times.

Now my question is I know my OCZ Platinum EL Rev 2's aren't godly memory compared to everyone elses OCZ Platinum EL's out there yet I see everyone running around the formula above. Is there a reason I shouldn't run it at a number lower than that? Also see people with DDR2 modules running the tRAS super low. Just looking to better my knowledge on memory timings.

Qubix said:

I have a question about Tras timing. DFI-Street Memory guide for upper end memory says to take CAS + tRCD + (0.5 or 1.0) = tRAS. My CAS is 2.5 and tRCD is 3 so that would be about 6-6.5 (7 rounding up) with lower = faster. Experimented with my memory the other day and found I could take my tRAS all the way to 0 and memtest would not make a single error. Even had it running Stress Prime to stress RAM for couple hours. It appeared 0 was slightly slower than 6 in Super Pi but 1 was the sweet spot and gave me the fastest times.

Now my question is I know my OCZ Platinum EL Rev 2's aren't godly memory compared to everyone elses OCZ Platinum EL's out there yet I see everyone running around the formula above. Is there a reason I shouldn't run it at a number lower than that? Also see people with DDR2 modules running the tRAS super low. Just looking to better my knowledge on memory timings.

Click to expand...

Try testing with Superpi-mod. You are just testing for stability, not speed.

with tRAS, you're better high than low...

memory latency is tough to wrap your mind around, but i'll see if i can use the book analogy....



you and your friend want to play a game: he's going to tell you a page number and a paragraph number and you're going to find it as fast as you can. and he'll give you 10 seconds to get to the right page/paragraph before he gives you a new page/paragraph (tRAS).

so you start with the book open. lets say, to page 87.

your friend says "219, 5." which means on page 219 find the 5th paragraph.

what do you do? first, it takes you a second to figure out which way to go (tRP). 219 is higher than 87, so once you figure out which way to flip the pages, it takes you a few seconds to get to page 219 (tRCD). once you're there, it takes a second or two to find the 5th paragraph (tCAS). finally, you're at 219, 5.

so in the example:
tRP - RAS Precharge delay is how long it takes to figure out which way to go to get to the right page. its the equivalent of the time it takes to erase the active row from cache to make room for a new row.
tRCD - Row Access Strobe to Column Access Strobe delay is how long it takes to flip to the right page, or how long it takes to access the correct row in memory.
tCAS - Column Access Strobe latency is how long it takes to locate the paragraph, or to locate the correct column where the data is.

tRAS is referred to as a latency, but its not a latency in the way tRP, tRCD and tCAS are. tRAS is more like a timer. its the minimum time before a new page/paragraph (new row) can be given.

which is why setting a tRAS too low will cause problems. imagine if your friend said "219, 5" and when you were flipping past page 200 he said "91, 3" and then as you got to page 91 he said "347, 1."

thats no fun. so its better to set a higher tRAS than you need than a lower one. better to have a few ticks extra than too few.

the general rule of thumb is to set a tRAS equal to your CAS + tRCD + 2 (or higher). that way you're not corrupting data in memory by only partially reading/writing it.

hope that made sense...

also note that tRP and tRCD come into affect only when the column needed is not in the already activated row. so, to stick with our example, if you're on page 87 and your buddy says "87, 7" you only have to find the 7th paragraph on the page you're already on. so CAS latency is always a factor. this is why tRP and tRCD dont have as large of an effect as CAS latency does. the overall latency relies greatly on the CL, which is why maintaining CL2 at all times, and all speeds is where the money's at

Jmag034 said:

with tRAS, you're better high than low...

memory latency is tough to wrap your mind around, but i'll see if i can use the book analogy....

Click to expand...

Great explaination. Also see Tref
http://www.overclock.net/faqs/96478-what-effect-tref-overclocks.html

Thank you, very well explained, sir.