ddr500+dfilanparty HELLPPP!

just bought some ddr it's 1gb samsung ucccx2 rated at pc3200 but the guy i bought them from ran through memetest at 255 w/ 3-4-4-9 timings at 2.65 volts. i ran it through memtest and didn't get errors for over 6 hrs but it won't booot windows at those speeds i'm running and opty144 @3ghz w/ 1.5v . these are my memory settings can any one help tweak the memory settings or did i just get some bum ram.

DRAM Voltage - 2.8v i have to set the voltage to 3.2v to boot into windows
Memory Divider - 3:4
Command Per Clock - On
CAS Latency Control (TCL) - 3
RAS Latency Control (Trcd) - 4
Min RAS active time (Tras) - 9
Row Precharge Time (Trp) - 4
Row Cycle Time (Trc) - 15
Row Refresh Cycle Time (Trfc) - 17
Row to Row Delay (Trrd) -3
Write Recover Time (Twr) - 3 Bus Clocks
Write to Read Delay (Twtr) - 2 Bus Clocks
Read to Write Delay (Trwt) - 3 Bus Clocks
Refresh Period (Tref) - 3120 Cycles
Write CAS Latency (Twcl) - 1 Bus Clocks
DRAM Bank Interleave - On
DQS Skew Control - Default
DQS Skew Value - 0
DRAM Drive Strength - 8
DRAM Data Drive Strength - 4
Max Async Latency - 8ns
Read Preamble Time - 6ns
Idle Cycle Limit - 16
Dynamic Counter - Enabled
R/W Queue Bypass - 8
Bypass Max - 4
32 Byte Granularity - auto

i think your just asking too much out of pc3200 .. its only supposed to run at 200mhz.. im suprised it runs at 255 .. maybe go to 3-4-4-10 if you can.. and at 3.2v .. you better put a little fan on those suckers

I agree with what jordon said, However, if it has Samsung UCCC chips, then most likely, it *can* run DDR500... what are the stock, PC3200 timings on them? if they're somewhere around 2-3-3-3, 2-2-2-5, or 2.5-3-2-5, most likely, they have a good chance of 250Mhz+.. You might want to bump up your chipset voltage to see if that helps any. Heres what I would recommend trying:

DRAM Voltage - 2.9 w/ +.03v enabled
Memory Divider - 3:4
Command Per Clock - On
CAS Latency Control (TCL) - 3
RAS Latency Control (Trcd) - 4
Min RAS active time (Tras) - 10
Row Precharge Time (Trp) - 4
Row Cycle Time (Trc) - 12
Row Refresh Cycle Time (Trfc) -18
Row to Row Delay (Trrd) -3
Write Recover Time (Twr) - 3 Bus Clocks
Write to Read Delay (Twtr) - 2 Bus Clocks
Read to Write Delay (Trwt) - 3 Bus Clocks
Refresh Period (Tref) - 3120 Cycles
Write CAS Latency (Twcl) - 1 Bus Clocks
DRAM Bank Interleave - On
DQS Skew Control - Default
DQS Skew Value - 0
DRAM Drive Strength - 8
DRAM Data Drive Strength - 4
Max Async Latency - 8ns
Read Preamble Time - 6ns
Idle Cycle Limit - 16
Dynamic Counter - Disabled
R/W Queue Bypass - 8
Bypass Max - 4
32 Byte Granularity - auto
DRAM Speed -Normal