RAM timings, what are they and what do they do? A bit of info

[RSDXzec]

RAM is the heart and soul of your overclock.
You may have noticed that RAM has various timings on it, but what do they do?

Here's a bit of info that can help you out.

The timings are as follows:

tRAS (Row Access Strobe): This is the amount of time between a row being activated by Precharge and deactivated. The lower the value, the faster the performance, but if its too low it may cause data corruption.

tWRT (Write Recovery Time): The timing that determines the delay between a write command and a precharge command is set to the same Bank of memory.

tWTR (W to R termination turnaround): The Write to Read time is the number of clock cycles between the last write data pair and the subsequent READ command to the same physical block.

tRCD (RAS to CAS access): Its the amount of time in cycles for issuing an active command and the read/write commands.

tRRD (RAS to RAS Delay): Its the amount of cycles it takes to activate the next bank of memory. The lower the better performance but it may cause instability.

tRP (Memory Bank switch): The row Precharge time is the minimum time between active commands and the read/writes of the next bank on the memory module.

tRWT (R to W turnaround): its the amount of cycles for the command to be recieved.

tRDRD (R to R timing) its the number of clock cycles between the last read and the subsequent read command to see the same physical blank.

tRC (Row Cycle Time): its the minimum time in cycles it takes a row to complete a full cycle. tRC = tRP + tRAS. If its too short, it can cause data corruption. If its too high it causes loss in performance.

tWRD (W to R Command Delay): its the amount of cycles required between a valid write command and the next read command. A lower cycle time increases performance but may cause instability.

tWRWR (W to W timimg): its the number of clock cycles between the last write and the subsequent write command to the same physical blank.

tCL (CAS Latency): The CAS latency is the time (in clock cycles) that elapses after the memory controller sends a request to read a memory location and before the data is sent to the module's output pins. This value cannot be changed.

tCPC (Command per clock): sets the command ate for the memory controller. This value cannot be changed.

So hope this helps all the overclockers out there!!!

Have fun overclocking!!!:beer:

[TranceBear]

Good post. This may help some of the FNG's with memory info.

[redduc900]

In addition to the definitions, maybe you could also explain what each of these terms means...

Clock Cycle
Row
Precharge
Write Command
Read Command
Active Command
Command Rate
Strobe / Row Access
Physical Block

... just to name a few. To the average computer user that's just getting into overclocking, it would be helpful if he or she was able to understand what terms like "This is the amount of time between a row being activated by Precharge and deactivated" actually means in layman's terms. So I think a good definition of some of the terminology used would be helpful to not only beginners, but to seasoned overclockers as well.

[Cluster]

Not to crap on this, but some of that is pretty vague, and some of it is just wrong. Most of the info you find scattered around the web, is a bit of both. I'll point out some of this.

tRAS - has little to nothing do with performance. The latency overlaps with CAS and RAS latency, and any memory operations. If there is more than a single memory op on the same row (which is very common), than tRAS is nil.

tRP has nothing to do with switching banks. Its the minimum time between the end of CL after a CAS signal before the row can be deactivated. It overlaps with the memory operation in progress. The minimum amount of latency from this setting is always tRP - 1 because every memory operation takes at least 1 clock. Most memory ops take more than this, and as such tRP little if ever has any affect.

tRC is kind of a mix of tRAS and tRP, and is pointless to set at less than the sum of these two. Its the minimum time between activating a row, and activating the next row.

To clarify the difference between these 3 a bit. RAS being row activation, -RAS being row deactivation. tRAS is the minimum time between RAS and -RAS, tRP is the minimum time between -RAS and RAS, tRC is the minimum time between RAS and RAS. For the most part they all overlap with regular memory operation, and are only in place to keep rows from being activated/deactivated to fast.

tRCD is the time from the RAS signal being sent before the CAS signal can be sent. Memory is activated first by row, then column. If the operation is being performed on an already activated row, then no RAS signal is necessary, and only the CAS is sent for the new column. This is basically identical to CL, only for RAS signals instead of CAS. Your likely to have to have better success setting tRCD lower than CL though for two reasons. Rows are not activated as much as columns. Because activation goes row -> column, the memory operation does not begin until CL has passed. If the operation begins before the CAS signal has time to complete(your CL is too tight), then you will get errors. Technically RAS/CAS should take the same time to complete, and it would seem pointless to set tRCD to less than CL, but because of these two points, you can sometimes get away with a tighter tRCD.

Again, not meaning to crap on this at all, but there is just far too much vague/wrong information on memory timings.

And, i have a guide running on mem timings thats being updated with the best information i can get my hands on. I have some emails going out to different memory companies to see if i can get some _exact_ information on the things like tRRD/tWTR as most of the information on the web is vague at best.

Ram Timing Guide (http://www.ocforums.com/showthread.php?t=588547)

Clock Cycle

Ram operates at a frequency like your CPU. Ram Frequencies range from 100-400mhz. (Dont confuse ram frequency with the DDR nonsense, DDR2-800 is 200mhz, DDR2-1066 is 266mhz). Divide this number by 1000 and you'll get the time each clock cycle takes. 200mhz = 5ns. Multiply this time by the number of clocks you set your timings to to get the 'real' latency. Cas 3 @ 200mhz = 15ns Cas Latency.

Row

Memory is arranged in a matrix of rows and columns. Ideally ram would only have 1 row, but this causes scalability problems. Multiplexers on ram modules take the incoming address from the memory controller and map it into a row/column address that it can understand to find exactly which cell is the beginning of that address.

Precharge

When a row needs to be deactivated, in order to select a new row, the precharge time allows for the deactivation to complete before the new RAS signal is sent to select another row.

Write Command
Read Command

Memory has two modes of operation, Read, which sends data from the memory cells, through an amplifier (the charge in a memory cell is very very small), and then forwards it to the data pins for transmission to the memory controller. Writing requires taking data off the data pins and pushing it to the cells capacitor. Writing operations generally need more time to complete or else the amount of charge that was put into the capacitors, for those cells that are needed to represent a 1, will not be suffecient enough before the ram is refreshed, and thus the value of that cell will become 0, and the data corrupt.

Active Command

There are two commands used for activation. Once the multiplexer has figured out which row/column the address given to it belongs to, it activates the memory cell, if not done so already (this is what Command Rate is), then lowers the RAS line, which activates the row that the multiplexer has selected, after tRCD, the CAS line is lowered, activating the column that was selected. This is activation.

Command Rate

Memory modules are made of multiple chips. Just like the need to select a row/column pair, there is also a need to select the chip. The command rate is how long it takes to activate the chip. This activation is not performed very frequenctly, and up until recently, was always 1 clock cycle. With ram speeds increasing, there was a need to have this operation take two cycles. For DDR-800+ its best to have this at 2T, its not going to effect performance, but will affect stability.

Strobe / Row Access

See Activate Command.

Physical Block

See Command Rate

[RSDXzec]

Not to crap on this, but some of that is pretty vague, and some of it is just wrong. Most of the info you find scattered around the web, is a bit of both. I'll point out some of this.

tRAS - has little to nothing do with performance. The latency overlaps with CAS and RAS latency, and any memory operations. If there is more than a single memory op on the same row (which is very common), than tRAS is nil.

tRP has nothing to do with switching banks. Its the minimum time between the end of CL after a CAS signal before the row can be deactivated. It overlaps with the memory operation in progress. The minimum amount of latency from this setting is always tRP - 1 because every memory operation takes at least 1 clock. Most memory ops take more than this, and as such tRP little if ever has any affect.

tRC is kind of a mix of tRAS and tRP, and is pointless to set at less than the sum of these two. Its the minimum time between activating a row, and activating the next row.

To clarify the difference between these 3 a bit. RAS being row activation, -RAS being row deactivation. tRAS is the minimum time between RAS and -RAS, tRP is the minimum time between -RAS and RAS, tRC is the minimum time between RAS and RAS. For the most part they all overlap with regular memory operation, and are only in place to keep rows from being activated/deactivated to fast.

tRCD is the time from the RAS signal being sent before the CAS signal can be sent. Memory is activated first by row, then column. If the operation is being performed on an already activated row, then no RAS signal is necessary, and only the CAS is sent for the new column. This is basically identical to CL, only for RAS signals instead of CAS. Your likely to have to have better success setting tRCD lower than CL though for two reasons. Rows are not activated as much as columns. Because activation goes row -> column, the memory operation does not begin until CL has passed. If the operation begins before the CAS signal has time to complete(your CL is too tight), then you will get errors. Technically RAS/CAS should take the same time to complete, and it would seem pointless to set tRCD to less than CL, but because of these two points, you can sometimes get away with a tighter tRCD.

Again, not meaning to crap on this at all, but there is just far too much vague/wrong information on memory timings.

And, i have a guide running on mem timings thats being updated with the best information i can get my hands on. I have some emails going out to different memory companies to see if i can get some _exact_ information on the things like tRRD/tWTR as most of the information on the web is vague at best.

Ram Timing Guide (http://www.ocforums.com/showthread.php?t=588547)

Clock Cycle

Ram operates at a frequency like your CPU. Ram Frequencies range from 100-400mhz. (Dont confuse ram frequency with the DDR nonsense, DDR2-800 is 200mhz, DDR2-1066 is 266mhz). Divide this number by 1000 and you'll get the time each clock cycle takes. 200mhz = 5ns. Multiply this time by the number of clocks you set your timings to to get the 'real' latency. Cas 3 @ 200mhz = 15ns Cas Latency.

Row

Memory is arranged in a matrix of rows and columns. Ideally ram would only have 1 row, but this causes scalability problems. Multiplexers on ram modules take the incoming address from the memory controller and map it into a row/column address that it can understand to find exactly which cell is the beginning of that address.

Precharge

When a row needs to be deactivated, in order to select a new row, the precharge time allows for the deactivation to complete before the new RAS signal is sent to select another row.

Write Command
Read Command

Memory has two modes of operation, Read, which sends data from the memory cells, through an amplifier (the charge in a memory cell is very very small), and then forwards it to the data pins for transmission to the memory controller. Writing requires taking data off the data pins and pushing it to the cells capacitor. Writing operations generally need more time to complete or else the amount of charge that was put into the capacitors, for those cells that are needed to represent a 1, will not be suffecient enough before the ram is refreshed, and thus the value of that cell will become 0, and the data corrupt.

Active Command

There are two commands used for activation. Once the multiplexer has figured out which row/column the address given to it belongs to, it activates the memory cell, if not done so already (this is what Command Rate is), then lowers the RAS line, which activates the row that the multiplexer has selected, after tRCD, the CAS line is lowered, activating the column that was selected. This is activation.

Command Rate

Memory modules are made of multiple chips. Just like the need to select a row/column pair, there is also a need to select the chip. The command rate is how long it takes to activate the chip. This activation is not performed very frequenctly, and up until recently, was always 1 clock cycle. With ram speeds increasing, there was a need to have this operation take two cycles. For DDR-800+ its best to have this at 2T, its not going to effect performance, but will affect stability.

Strobe / Row Access

See Activate Command.

Physical Block

See Command Rate

See this is what people do when they have nothing better to do.
Geeze im just posting a little guide you dont have to be so annoying:p.

Thanks reduc for your ideas, but i wont bother since Cluster here thinks he's so good, just ask him, why doesnt he just help everyone out if he's so PRO.

All i tried to do was give a lil info, GOSH, some people.

[Cluster]

Not being annoying or thinking im better by any means. I simply have a few years of experience with the subject, and have done alot of research, including the dozens of white papers and tech specs i've been through.

Nothing wrong with posting some info, its what the boards are here for, but copy/pasting the same vague/wrong info that is all over the web... did you not expect someone to correct you?

And as a matter of fact, i help people as much as i can, and have been doing so on these boards for over 7 years now. Hope i helped _you_ in understanding your own information, and if you have any questions, i'd be more than happy to answer them :)

[RSDXzec]

to be honest, i didnt copy and paste off the net, i read a manual and tried to explain it a bit better. But its good to know that you help ppl out with this issue.