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- Jul 1, 2008
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I'm working on overclocking some DDR3s, and I'm hitting the timing numbers one at a time. Right now, I'm on tWTR, and it occurs to me that I can't be sure that any number is safe bases on stress testing.
tWTR is the time delay between issuing a write and when it's safe to issue a read to the same bank on the open row. This is due to there being internal pipelining in the RAMs for storing words into the row buffer. There is similar pipelining for reads, but that's visible to us as CAS latency. For writes, once the northbridge has handed the data off to the RAM, there is no longer any need to be concerned about the data, and internal pipelining in the RAM chips is mostly hidden.
The tWTR timing constraint is there to ensure that the last write makes its way into the buffer before a read is issued, JUST IN CASE the host controller would try to read the same address that it just wrote. As far as I can guess, the effect of issuing a read of some address too soon after writing it is that you'd get stale data out of the RAM.
So when would we ever see this? Any time any software would read some address it just wrote, this would be satisfied by the L1 cache (or straight out of the pending write queue). So the only way for software to see this would be if all caches were strictly disabled, and I somehow, I got the impression that technically, you can't totally disable the L1 caches on Intel processors.
Another possibility would be if some DMA transaction ended, immediately followed by a read by the CPU or another DMA controller of the same address. The thing is that DMA transactions are typically followed by an interrupt signal, and the latency from assertion to start of the ISR is ages by comparison to tWTR.
Still, there's that 1 in a trillion situation where it could happen, so I want a safe number.
And yet, there is some value in finding the lowest value. Decreasing it would allow the RAMs to service reads after writes on the same row, as long as there is no overlap in addresses between writes and reads.
Thoughts? Suggestions?
One suggestion to self: Run various performance tests at different values of tWTR to see if it makes any measurable difference. Northbridge chips may typically optimize the ordering of read and write bursts to minimize the impact of things like this. Maybe. But then again, if that were the case, CAS latency would also have less impact than it seems to.
Thanks!
tWTR is the time delay between issuing a write and when it's safe to issue a read to the same bank on the open row. This is due to there being internal pipelining in the RAMs for storing words into the row buffer. There is similar pipelining for reads, but that's visible to us as CAS latency. For writes, once the northbridge has handed the data off to the RAM, there is no longer any need to be concerned about the data, and internal pipelining in the RAM chips is mostly hidden.
The tWTR timing constraint is there to ensure that the last write makes its way into the buffer before a read is issued, JUST IN CASE the host controller would try to read the same address that it just wrote. As far as I can guess, the effect of issuing a read of some address too soon after writing it is that you'd get stale data out of the RAM.
So when would we ever see this? Any time any software would read some address it just wrote, this would be satisfied by the L1 cache (or straight out of the pending write queue). So the only way for software to see this would be if all caches were strictly disabled, and I somehow, I got the impression that technically, you can't totally disable the L1 caches on Intel processors.
Another possibility would be if some DMA transaction ended, immediately followed by a read by the CPU or another DMA controller of the same address. The thing is that DMA transactions are typically followed by an interrupt signal, and the latency from assertion to start of the ISR is ages by comparison to tWTR.
Still, there's that 1 in a trillion situation where it could happen, so I want a safe number.
And yet, there is some value in finding the lowest value. Decreasing it would allow the RAMs to service reads after writes on the same row, as long as there is no overlap in addresses between writes and reads.
Thoughts? Suggestions?
One suggestion to self: Run various performance tests at different values of tWTR to see if it makes any measurable difference. Northbridge chips may typically optimize the ordering of read and write bursts to minimize the impact of things like this. Maybe. But then again, if that were the case, CAS latency would also have less impact than it seems to.
Thanks!
