i would like to make one thing clear

many people thinks lower cas rating memory is better than higher cas mem but higher speed

E.G 1333 MHZ @ 8-8-8 vs 1600 MHZ @ 9-9-9

so someone would say, they both give enough bandwidth to feed an i7 on stock
so they say the 1333MHZ mem is better because of lower latency

THIS IS NOT TRUE!

those numbers are the clocks to wait till the modules can retrieve the data

but remember also that on the 1600MHZ ram the clock speed is higher
resulting in even less effective latency
1333MHZ mem has 6 uS while 1600MHZ has 5 uS

if i am not wrong (but i shouldn't ;p)

well u comparing something like a 2.6Ghz quad core vs a 4.2Ghz P4

SuperMiguel said:

well u comparing something like a 2.6Ghz quad core vs a 4.2Ghz P4

Click to expand...

i know. but there is ppl who does the same thing without knowing what i just wrote XD

I know waht u mean... same thing with a 78gb 15000RPM hd compared with a 250GB 5200RPM

Higher frequency higher latency has been better for Intel platforms than
lower frequency lower latency for some time now. What I seem to remember
about older AMD64 platforms is the opposite, favoring lower latency over higher
frequency. Haven't really looked into the AMD side recently.

Fortunately, for most normal apps, RAM frequency and latency are rather
unimportant, so long as they aren't too slow.

I guess I usually would favor higher freqeuncies over lower latency for the reason
that once the data is found, it is pumped out of the DRAM much faster. Bear in mind
that the DRAM will burst out 4 or 8 64-bit sequential data, before a new column
address (at minimum) is needed for the next read or write.

Since you mentioned i7, a bit of food for further thought.

The address bus on a DRAM is multiplexed, and in simple terms, there are page,
row and column addresses that must be sent over separately on a shared bus.

An IMC equipped CPU has the opportunity for optimization, since the CPU has most
intimate knowledge of what data is needed next or in the future, the IMC could optimize
prefetch of data to minimize the number of row address strobes and page accesses.

You should really put up some numbers to support your thinking. It is VERY common to see the exact opposite assertion you are making. bz2klag has it right. I can post up some numbers tonight to show bandwidth differences.