Interesting cache question...

Just today I was thinking about the L1 and L2 caches on chips and how I would just love for people to stick more L1 on. The reason is that the L1 cache is supposed to be faster than the L2. However, after thinking about it for a moment, I realized that shouldn't be.

Back in the old days of cache, you had your L1 on chip (at chip speed) and your L2 on the motherboard (at FSB speed). Now, under this situation, the L1 cache would most cirtanly be faster than the L2. However, in the recent history of computers (isn't it all recent?), chip manufactures started putting the L2 on die with L1.

Now, I know that some chips have half speed L2, however, there is full speed L2 cache on some chips too. In this case, since the L1 is running at chip speed, and so is the L2, why would the L1 be any faster than the L2?? Would the cache latency of the L2 be the reason? And if so, wouldn't that mean that on my celeron (mendicino core) the L1 IS just as fast as L2 (since the L2 cache latency is 0)??

Man of strange epiphanies...
JigPu

Well, first of all, the chips with the half speed L2 dont have the L2 on-die. Its on the CARTRIDGE that the core is on. I'm not sure about the answer, i guess its because its faster to access L1 because there is less L1 to access.

I didn't know that! Guess that when it is in the same package, it just seems on die.
Oh... I can see how the L1's smaller size would make it accessable faster. Though I don't know if in reality it would.... Anybody else wanna back that up?? Or perhaps another idea?

JigPu