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First SIMMs, now DIMMs, what's next? QIMMs?

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star882

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Jan 6, 2003
In the past, I remembered that when the Pentium first came out, you had to install SIMMs in pairs.
Then they made DIMMs that can be installed one by one on a Pentium(I actually still have one of those Pentiums).
Now, the Britney is out, and you have to install DIMMs in pairs, and the same thing goes with dual-channel P4 boards.
What's next? QIMMs(Quad Inline Memory Module)?
BTW, They say that the 128-bit memory controller in the Britney is to help reduce "digital rush hour".
 
Who knows?

A little history as to the nameing....

Originally after there were individual DRAMS the first widely used bundling was a SIMM

The first SIMMS (Single inline memory module), where 30 pins or 16bits which had to be installed in pairs on a 32bit motherboard, like 386's, 486's, etc.

Then came 72pin SIMMS, which were 32bits in width so a 32 bit memory bus only required one simm.

Then along came DIMMS, which are 64bits wide so that the current 64bit wide memory databus on machines only needs one memory module.
 
"rimms?"
The Britney is designed to use DDR RAM, making it use RDRAM will require significant core design changes(integrated DDR controller).
Besides, AMD somehow doesn't want to use RDRAM.
Oh, and speaking of the integrated DDR controller, how does DMA(Direct Memory Access(accessing RAM without the data going through the CPU)) work in Britney machines?
 
how does moving the MC prohibit CPU access, it would be faster CPU access as the integrated controller provides a much lower latency.

is britney some new AMD chipset or something, you seem to like saying it alot so it must be something important - but god damn thats one stupid name for anything
 
"how does moving the MC prohibit CPU access, it would be faster CPU access as the integrated controller provides a much lower latency."
I understand the part about the lower latency, but how do other devices(like a hard drive controller or AGP video card) get access to the RAM without the data going through the CPU?
"is britney some new AMD chipset or something, you seem to like saying it alot so it must be something important - but god damn thats one stupid name for anything"
The Britney is a CPU with part of the north bridge integrated onto the core(the other part of the north bridge is often referred to as the "south bridge" in Britney machines(one time, I heard an "expert" in computers who has not yet heard about the Britney say, "That's a nice machine, but why is there Britney printed onto the north bridge heatsink?"(the small chip with the small heatsink is the south bridge, the north bridge is inside the CPU))).
 
star882 said:
Besides, AMD somehow doesn't want to use RDRAM.

Before, AMD couldn't make use of RDRAM's bandwidth. (P3's certainly can't.) Now, RDRAM is about to fall behind DDR, and Intel has phased out RDRAM. Plus, RDRAM costs more. RDRAM would be a bad bet for AMD.
 
star882 said:
The Britney is a CPU with part of the north bridge integrated onto the core(the other part of the north bridge is often referred to as the "south bridge" in Britney machines(one time, I heard an "expert" in computers who has not yet heard about the Britney say, "That's a nice machine, but why is there Britney printed onto the north bridge heatsink?"(the small chip with the small heatsink is the south bridge, the north bridge is inside the CPU))).

I'd like to integrate my southbridge into Britney.;)
 
So "Britney" is a chip, and not a chipset? Or is it? And is "Britney" for AMD or Intel? And wtf came up with the bright idea of naming this "Britney"?!?!

I guess I missed something...
 
"I'd like to integrate my southbridge into Britney."
Well, if they do, power usage will go up(the Britney already consumes 130w, why make it worse?).
 
"Britney as in Britney "Look-at-my-ta-tas" Spears?"
LOL, My friend Tom Stage said that Spears(Simultaneous Parallel Execution ARchitecture System) is just a fancy name for a vector unit(this started in a private chat room BTW).
 
I E-mailed my friend Caitlin Williams about this and she said,
"Perhaps a more logical way of thinking is that the memory controller is not integrated onto the actual CPU, but they do both now reside on the same chip.
So the memory controller is still independantly accessable (through the hypertransport link), as it would be if it were a seperate chip."
 
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