- Thread Starter
- #81
Without doing further research on the internet, this is from a post in the sticky
A64 CPUs, chipsets, motherboards
in case you have not seen it.
A64 CPUs, chipsets, motherboards
in case you have not seen it.
Originally posted by hitechjb1
About Rev E and SSE3 instructions
Rumor is a new revision E 90 nm 939 (Venice ?) with SSE3 support is coming (2005 ?).
http://anandtech.com/mb/showdoc.aspx?i=2264&p=3
From this article which reported AMD's chief Hammer Architect's (Kevin McGrath) presentation, at Stanford University
http://techreport.com/onearticle.x/6363
from above article said:...
The enhancements include power reductions (gained by using slow but less leaky transistors in non-critical paths) and speed improvements (by using fast but leaky transistors in critical paths). Also, the processor halt and stopclock states have been improved, reducing some unnecessary work previously conducted during these states, resulting in a savings of several hundred milliwatts. Like the Pentium 4, future Hammer chips will feature on-die thermal throttling to cool themselves down if certain temperature limits are reached.
Performance-wise, the big news is the addition of SSE3 instructions, which accelerate a number of different types of computation, including video encoding, scientific computing, and software graphics vertex shaders. (For more on SSE3, see our Prescott review.) Beyond SSE3, the updated Hammer core will convert the LEA instruction, under certain circumstances, into an ADD instruction, which has only a single cycle of latency. AMD's design mavens have also added additional write-combining buffers to the chip, so it can combine up to four streams of non-cacheable writes, up from two. Hammer's data prefetch has been improved, as well.
...
Rumor is there will be additional metal layers added for the E core. In general terms, extra metal layers are used to
- improve power distribution, i.e. less voltage drop for a given current or more current to more devices
- improve connectivity to package I/O, i.e. more package pins
- reduce signal RC delay, hence potentially higher clock frequency
- reduce clock skew, hence potentially higher clock frequency
- provide more flexible communication paths between functional units and multiple cores
- improve signal integrity
...
So the net is to enable more complex architecture and logic functions, multiple cores, higher socket pin count, higher clock, more devices, ....
About SSE3 Instructions:
http://www.intel.com/technology/itj/2004/volume08issue01/art01_microarchitecture/p06_sse.htm