AMD prepares dual-core 45nm surprise.

Firestrider · Feb 17, 2009

AlabamaCajun said:
AMD is doing what most smart companies are doing. Call it maximizing product or productivity increases. It comes down to using as much as produced as you can and I see no problem with that. You get the tech you want at the lowest price of all performance chips out there. The company recovers the cost of expensive silicon and processes. We use to watch houses being built. Workers would cut a 5 foot piece of sheetrock or plywood and throw out or burn the other 3 feet. Why waste so much material? The salvage business is one huge business today and some are the only companies still holding up. If AMD can pick out the chips with good NB and cache that have 2 or 3 cores operable then more power to them.

This argument has come up too many times. Pick One!
Neha is quite different and it may not run with a lame core.
Intel either wastes a lot or they are unable to.
Lamed Nehas are being sold to companies or countries as duals and not saying what process they are.
They make great clay pigeons "Pull"

Yeah you are right. I have no idea what Intel does with broken Nehalems or if they are even salvagable, if they aren't, then AMD has a much smarter design economically.

Zurvan · Feb 17, 2009

Rick James said:
Can someone answer me this. Whats better? 8 megs of L2 cache or 8 megs of L3 cache? Ok.. Then why?

L2 access is 10-14 CPU cycles, L3 is 35-40 CPU cycles. Atleast 3x slower.

Rick James said:
Then why doesn't amd use 8 megs of L2 instead of L3?

Architecture(K10,Nehalem) demands a shift. Initially L2 was large, common cache for all the cores. Now hierarchy has increased by one step and L2 is for each core separate and L3 is common,shared. As cores increase, this design principles seems to work better/cheaper.

BTW, its seeing the L3 cache I guessed this is Deneb-cut and not original Dual. Regor will have 1 MB L2 per core, no L3. Once we see the TDP , this will be confirmed.

Caviman2201 said:
really makes you wonder if they're having problems with the 45nm yields...

Yep. Since they are introducing a new line, I guess there are lots of chips with 2 faulty cores.

Archer0915 said:
I don't think it is as bad as ppl think it is just easier to cut cores and sell as dual or tri at a lower rate. There is that whole economic thing to consider and the fact is there is not much cost difference in the manufacturing process between the two.

I doubt that is happening. Cost of production for each chip is same - regardless its a dual-triple or quad core.
If they wanted to sell products at a cheaper pricepoint, they would try producing a cheaper derivative from startup- which is already marked on the roadmap. You might argue about increased R&D, but I think creating a native dual core design based on the already existing K10.5 shouldnt be that difficult. Just have a look (chart courtesy anandtech)

Just imagine - Deneb Dual core vs E5X00 :bang head

Kuroimaho · Feb 17, 2009

Caviman2201 said:
really makes you wonder if they're having problems with the 45nm yields...

That's what I asked when they launched the triples so early compared to PHI.
So we likely have an answer with these duals but their quantity will tell, if these will be scarce yields might be still good, just AMD does not want to sit on inventory these troubled times.

Firestrider said:
Yeah because Intel was aiming at making a server processor with Nehalem thus needed to introduce L3 cache. I think people would be happier on desktop with the IMC, QPI, and large quick access L2 cache.

L3 is also used to communicate between the cores, while L2 isn't shared and because L3 is inclusive it has to be bigger than the combined L2.

Firestrider said:
Intel (Nehalem) has the same structure as the Phenoms but I don't see one sold as a triple or dual core. Intel could be trashing the processors with faulty cores though, I don't know.

There are dual core nehas for servers, so who knows, but there is no doubt they will use it in the future. Intel Can Create Processors with Odd Number of Cores Thanks to Recovery Scheme

It makes sense to do it, but no doubt it would be better if there were no need to sell quads for half the price.
The real question is what will be the average selling price for Phenom 2 with these.

Firestrider · Feb 17, 2009

Zurvan said:
L2 access is 10-14 CPU cycles, L3 is 35-40 CPU cycles. Atleast 3x slower.

Architecture(K10,Nehalem) demands a shift. Initially L2 was large, common cache for all the cores. Now hierarchy has increased by one step and L2 is for each core separate and L3 is common,shared. As cores increase, this design principles seems to work better/cheaper.

BTW, its seeing the L3 cache I guessed this is Deneb-cut and not original Dual. Regor will have 1 MB L2 per core, no L3. Once we see the TDP , this will be confirmed.

Yep. Since they are introducing a new line, I guess there are lots of chips with 2 faulty cores.

I doubt that is happening. Cost of production for each chip is same - regardless its a dual-triple or quad core.
If they wanted to sell products at a cheaper pricepoint, they would try producing a cheaper derivative from startup- which is already marked on the roadmap. You might argue about increased R&D, but I think creating a native dual core design based on the already existing K10.5 shouldnt be that difficult. Just have a look (chart courtesy anandtech)

Just imagine - Deneb Dual core vs E5X00

Huh? Deneb/Shanghai has a die size of 285mm^2, Yorkfield has a die size of 214mm^2

Kuroimaho · Feb 17, 2009

Only the 12MB ones, the rest is as in the table and those are the ones AMD competes with I think.

terran2k · Feb 17, 2009

Smart move by AMD, excellent way to maximize profits, infact ever since the new head guy took over AMD, they've made a bunch of smart moves.

Firestrider · Feb 17, 2009

Ok, 214mm^2 - 164mm^2 = 50mm^2 for 6 MB of cache?

Even though the 12 MB Yorkfield's have 4 MB more cache then Deneb how are they using less die size?

Does the IMC and HyperTransport links really use that much die size or is there something I'm missing?

Caviman2201 · Feb 17, 2009

Kind of makes you wonder why AMD has pretty much abandoned native dual-cores... unless thats what Regor is expected to be...

Rick James · Feb 17, 2009

Why are the X3's competing against the E7's and not the E8's?

Edit - E7's - 1066 Bus, Half the Cache compared to the E8's

Kuroimaho · Feb 17, 2009

Firestrider said:
Does the IMC and HyperTransport links really use that much die size or is there something I'm missing?

Intel is quite proud that they make the most dense cache so they can threw in a little more or make the cpu smaller.
We also likely talk about 2 IMC (DDR2 and DDR3 but not a must), and more than one HT as Optys have more than one but the difference in size is too small to create a separate die for it.

Firestrider · Feb 17, 2009

Caviman2201 said:
Kind of makes you wonder why AMD has pretty much abandoned native dual-cores... unless thats what Regor is expected to be...

I think the original Phenoms should have been the same principle as Core 2 Quads. Two native dual-core MCM connected via HyperTransport.

Do we really see a benefit of having a single cache per thread and a shared cache for four threads?

Firestrider · Feb 17, 2009

Kuroimaho said:
Intel is quite proud that they make the most dense cache so they can threw in a little more or make the cpu smaller.
We also likely talk about 2 IMC (DDR2 and DDR3 but not a must), and more than one HT as Optys have more than one but the difference in size is too small to create a separate die for it.

As far as I'm aware 1 bit of SRAM requires 6 transistors. Is there any differentiation between AMD's and Intel's implementation? They are both manufactured on the 45nm process right?

Kuroimaho · Feb 17, 2009

Regardless of being made on the same node Intel has the size advantage.

At 45nm that cell size was 0.346 um^2 (for desktop processors, Atom uses a slightly larger cell), compared to 0.370 um^2 for AMD’s 45nm SRAM cell size.

Source

Archer0915 · Feb 17, 2009

I doubt that is happening. Cost of production for each chip is same - regardless its a dual-triple or quad core.
If they wanted to sell products at a cheaper pricepoint, they would try producing a cheaper derivative from startup- which is already marked on the roadmap. You might argue about increased R&D, but I think creating a native dual core design based on the already existing K10.5 shouldnt be that difficult. Just have a look (chart courtesy anandtech)

Just imagine - Deneb Dual core vs E5X00

I agree in principal and you are correct however I am saying that because costs are the same to use one core instead of 3 or 4 (different fabs)that depending on demand that an intentional murder of a quad may be a viable option to keep the boat afloat and keep production and money flowing. What I said about cost was using different cores ie. dual and tri.

Archer0915 · Feb 17, 2009

Oh one more thing if AMD can make enough bad parts to keep a flow of dual's and tri's than someone needs their arse kicked any engineer knows that if you can not repeat the process 99.XX% of the time in a high yield environment then you need your process re-evaluated. Some body missed out on black belt training and needs a course in TQM.

Particle · Feb 17, 2009

I'm not so sure. I've heard it said somewhere that TSMC often experiences yields under 80% for nVidia GPUs and that's considered the cost of doing business.

Archer0915 · Feb 17, 2009

Particle said:
I'm not so sure. I've heard it said somewhere that TSMC often experiences yields under 80% for nVidia GPUs and that's considered the cost of doing business.

I was generalizing but there is a base point that statement was not matter of fact but I would like to know what the real yield expectations are and if the problems are with the silicon or the process.

You know thinking about it what the hell is the problem? If it can be done right a majority of the time why is it not being done right every time?

And the generalization was mechanical manufacturing. Being that I have never worked with CPU's I should have left that number out.

hooflung · Feb 17, 2009

Intel does chip sampling too. The e4300 is a prime example of it. It has all the virtualization bits on die but its turned off. It also has 2mb of it's cache disabled.

Usually when the initial product comes to market its because of defects. If market demand goes through the roof they will start crippling it's big brothers to meet demand. A chip sold is a chip sold. It doesn't matter if they can meet market demand for every man woman and child on the planet, if people won't buy certain parts at certain pricepoints they will always make a cheaper product. Economic's 101.

AMD just also tend to sample their cores now like ATI did pre-buyout. If you can take 2 cores that don't work and sqeeze a product line out of it then why not? Its either that or the garbage bin.

Intel is also going to be doing that with their Neh. chips soon as Arstechnica stated last week. They will be harvesting cores for different products. IE, now intel has a chip that CAN be treated like this and not have the Celeron name to it.

Zurvan · Feb 17, 2009

Particle said:
I'm not so sure. I've heard it said somewhere that TSMC often experiences yields under 80% for nVidia GPUs and that's considered the cost of doing business.

LOL , what better do you expect with 1.4 billion transistors on a lame 65nm TSMC process ? The initial yields would have been far less.

Particle · Feb 17, 2009

Zurvan said:
LOL , what better do you expect with 1.4 billion transistors on a lame 65nm TSMC process ? The initial yields would have been far less.

Your response assumes that I'm somehow surprised or shocked by the information. I'm not. What I listed was a counter to the claim that 99.9% should be achieved for high volume lithography and that anything below should be considered faulty production (eg, time for an examination as to why things are going so badly). I'm not sure what you're laughing about.

AMD prepares dual-core 45nm surprise.

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