AMD prepares dual-core 45nm surprise.

Robbman said:

Since AM3 is backwards compatible with AM2+... makes no sense for them not to be...

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The reason I question is because I want AMD to make some [cheap] AM2+ Denebs available. For a business, I can imagine many reasons for it being not feasible for them, but as a customer, plenty would love them if they can set their prices lower than AM3 ones. The fact that they would work in AM2 boards is the key here, since most of AMDs consumer base is AM2, not AM2+/AM3.

Up until now, for months, the mass shipment Denebs have been only AM2+. They are also the highest speed Denebs which means those wafers are the highest bin. That inturn means these CPUs will also be the ones with the highest defects and the ones with the highest number of chips thrown away as waste. There is no other use for them. The amount of chips thrown away would be quite high (although not in huge volumes).

I would love if AMD lets you buy such chips with 1/2/3 cores and/or 2/4MB cache disabled. They'd be able to salvage plenty of "wasted cost" with profit. Most of the silicon is always fully functional but for some logic part whcih can easily be disabled. They can sell the leakage runaway chips (uber clocking but with high power) in one segment and the ultra low leakage (low clocking with minimal power) in another segment, to special customers. Heck, I'd buy plenty of such chips if they were available (without getting in trouble). Remove the K8 X2 45W, and throw one of these in. No need for formal specs and listing.

Alas! Dreams..

KTE said:

I would love if AMD lets you buy such chips with 1/2/3 cores and/or 2/4MB cache disabled.

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They let you, at least duals and triples, then there is the 810 with less cache.

+1 ^^^, the OEMs will get plenty of options but for now it's the first run which we are seeing in smaller quantities. The major production is coming.
Currently there are 7xxx and 8xxx chips in the middle and upper priced business and home boxen. Then they have access to all the Brisby line which run from 1.8G to 3.2G for low to high end oem boxen.

Kuroimaho said:

They let you, at least duals and triples, then there is the 810 with less cache.

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Those are the Socket AM3 salvaged Denebs which are available, you're right.

I'm speaking about Socket AM2+ salvaged Denebs here.

Most of the "wasted" silicon so far will be from the AM2+ Deneb wafers.

Same stepping, same rev, same die just different packaging, there are no AM2+ or AM3 wafers.

You might be right but I'll have to see the silicon specs to make sure, that both AM2+ and AM3 Denebs are exactly the same silicon. A few things don't add up. One of them that stands out is, AM3 Denebs have had many DDR2-1066 validation problems (which was one the delay reasons) on the same MBs that socket AM2+ Denebs don't have. Another is the Northbridge revision which would need to checked, since AM3 Denebs run the NB faster than AM2+ which wasn't possible for the AM2+ Denebs under the 125W envelope.

As for the DRAM controller, it was designed to run DDR3 from the beginning. I don't have the link at this time but the Barcelona core had the driver circuit from day one to handle the DDR3 encoding. I think the fact that DD3 was not coming into market as fast as though, AMD just pulled back and took advantage delaying the socket changes. From the Istanbul perspective on servers, it will still be DDR2 compliant allowing us to use our S1207 server board for even longer (Saweet). I think this early ability to run DDR3 may be to do with dual compatibility. The best path for those going to DDR3 is to get 1200 at tight arse latencies.

Bump Bump!

Anyone see any news about the duals.

Sidenote, these might unlock too

They are out in dual already?