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[O/C]Intel to Restrict Overclocking on Sandy Bridge

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This really would be AMD's time to shine.

They could start making better processors with lower heat output and a smaller form factor while being able to charge more if they allow for overclocking on said processors.
 
Different by design as in you have to buy an overclockable CPU, that's my guess.
We may not be a large segment, but we do exist, if half the people on this forum go to SB and buy unlocked CPUs at the current locked+$100 rate intel gets $44K, that's not bad, really.

It's in intel's best interests to charge more for unlocked CPUs and keep bus speed locked, just like it was in AMDs best interest back when HTref didn't OC as well. They had BE and non-BE for the same cpu, the BE just cost more.
Really Intel just has to make it hard, it doesn't matter if it's doable as long as the basic joe n00b can't do it effectively.
I can't see intel making it impossible, at some point someone will make a motherboard with a filter in the PLL lines, it catches the signal and raises it. The sata is on the chipset, it's uneffected, same for USB. The PCIe on die goes up, but the same chip could interface into the PCIe lines (ala Hydra) and drop the frequency back down to 100 to keep the GPUs happy.
It'd cost more, but it ought to be doable.

As James Bolivar DiGriz says: What man can lock and encode man can unlock and decode.
 
+1 Yeah now you will have to buy the k models and extreme. Did you read how there doing it this time, Intel has tied the speed of every bus (USB, SATA, PCI, PCI-E, CPU cores, Uncore, memory etc) to a single internal clock generator issuing the basic 100MHz Base Clock.
 
Intel had the writing on the wall as soon as Turbo Boost Technology was unveiled. Their marketing department will start saying every chip they make is overclocked automatically, which is technically true (anything with turbo boost, which will be almost every chip soon).

AMD is coming out with something similar soon.

We all got spoiled from the legendary Core2Duo series (4.0Ghz on stock voltage, yawn =D) and we'll have to work a lot harder to get those good overclocks. But that's the fun ;)
 
We all knew this would happen. Intel has never been a fan of overclockers because we can show how unjustified their prices are for extreme chips compared to a normal. AMD is soon to follow im sure...:bang head
 
Frankly, the headline and summary are over the top. Where's the quality control? At best, this is editorialising.

Deliberately restricting overclocking? Are you really sure that the sole and only reason Intel is reducing down to a single on-die clock generator is to thwart overclocking? Not to, say, simplify design and reduce cost? Because these seem like logical things to do, trending along with on-die memory controllers and the like.

In fact, the linked bit-tech article says as much, albeit in a breathless manner that assumes intention where I'd imagine there is none. This seems to be deliberately limiting overclocking in the sense that gravity deliberately interferes with my dreams of flying like superman.

I think we could have done a better job of objectively decoupling the editorialising (assuming certain dastardly intentions) from the reporting (the chips will do X). We're better than this.

It's certainly not the end of the day. "Normal" users get a cheaper chip, more of the system is on the chip (with presumably fewer failure modes as a result), and the rest of us can happily bypass the clock signals onboard. Big deal.

More accurate headline: Sandbridge on-die clock generator will likely break current overclocking methods.

OK, who the hell are you? Did you, in a past profession, have experience as a writer/editor?

I only ask because what you just said makes perfect sense and is an example of a much larger problem in all outlets of media/journalism (especially politics) and is something I think we should all be more cognizant of.

Thus, I would like to subscribe to your newsletter.

(edit*** Also, I forgot to add: in my experience, what you said usually comes from the mouth of a crazy old dude with tautologically infallible conspiracy theories about 9/11 and etc. Even if they're right... I mean... they're crazy. Surprisingly, your rant was quite reasonable.)
 
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we'll have to work a lot harder to get those good overclocks. But that's the fun ;)
I don't think it's going to be fun if Intel sets there engineers to make a chip that we can't overclock

The motherboard manufactures are going to have to come up with some magic engineering of there own and make a external clock generator that will separate USB, SATA, PCI, PCI-E, CPU cores, Uncore, memory etc. I'm guessing it would be before and after the DMI bus also memory and PCI-E that will send separate clock signals.

If Intel does this, it's going to cost allot of money to overclock, either you pay intel for the unlock multiplier CPU's or hope they can make $400+ motherboards to overclock.

I don't know where the fun is, if this happens.

QUOTE:This is because Intel has tied the speed of every bus (USB, SATA, PCI, PCI-E, CPU cores, Uncore, memory etc) to a single internal clock generator issuing the basic 100MHz Base Clock.

This clock gen is integrated into the P67 motherboard chipset and transmits the clock signal to the CPU via the DMI bus. This means there's no need for an external clock generator that used to allow completely separate control of all the individual hardware.
 
I betcha the DMI bus clock signal is the clock signal, it'd make sense given that the DMI is a PCIe bus with a new name.

I was talking to someone (ghost?) about the very first SB chip seen in the wild and how it looked like they were using PCIe directly for the bclk and how it'd be a major pain to OC. Wish i'd posted that convo back then, i'd look like an oracle or something now :p
 
I betcha the DMI bus clock signal is the clock signal, it'd make sense given that the DMI is a PCIe bus with a new name.

I was talking to someone (ghost?) about the very first SB chip seen in the wild and how it looked like they were using PCIe directly for the bclk and how it'd be a major pain to OC. Wish i'd posted that convo back then, i'd look like an oracle or something now :p

Direct Media Interface DMI, It provides for a 2GB/s bidirectional data rate.

It's much faster than the PCI E specifications because it handles all the south PCH traffic, all at the same time on intel specked boards.

Here is a old Link when it was only 10Gb/s:http://en.wikipedia.org/wiki/Direct_Media_Interface
 
I betcha the DMI bus clock signal is the clock signal, it'd make sense given that the DMI is a PCIe bus with a new name.

Like i said:


The current DMI is a 4x PCIe 2.0 link, which totals 2GB/s.
http://www.bit-tech.net/hardware/cpus/2010/04/21/intel-sandy-bridge-details-of-the-next-gen/1
Gotta keep in mind, a PCIe 16x 2.0 slot is a whopping 8GB/s of bandwidth.

PCIe 16x 2.0 slot is 16GB of bandwidth bidirectional.

The current DMI is a 4x PCIe 2.0, which totals 2GB/s bidirectional, Intel is using PCIe 1.0 speed standard 250 MB/s on the DMI bus on the ICH-10, P55

Anandtech LINK:http://www.anandtech.com/show/3574

Your still missing some things.;)

The PCIe 2.0 standard uses a base clock speed of 5.0 GHz, while the PCIe 1.0 version operates at 2.5 GHz


QUOTE: and posted on YouTube (see from 2mins onwards) confirms the fact that only a 2-3 per cent OC via Base Clock adjustments will be possible. This is because Intel has tied the speed of every bus (USB, SATA, PCI, PCI-E, CPU cores, Uncore, memory etc) to a single internal clock generator issuing the basic 100MHz Base Clock.

The base clock comes from a clock Generator in the PCH.

Thanks for the link, for sandy bridge:)
 
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OK, who the hell are you? Did you, in a past profession, have experience as a writer/editor?

I only ask because what you just said makes perfect sense and is an example of a much larger problem in all outlets of media/journalism (especially politics) and is something I think we should all be more cognizant of.

Thus, I would like to subscribe to your newsletter.

(edit*** Also, I forgot to add: in my experience, what you said usually comes from the mouth of a crazy old dude with tautologically infallible conspiracy theories about 9/11 and etc. Even if they're right... I mean... they're crazy. Surprisingly, your rant was quite reasonable.)

Uh, thanks?

I'm just a mathematician / scientist who wants us to be accurate. We have a great responsibility to our readership, who can sometimes tend to take rumours to be fact far too quickly. We're still seeing some of that in this thread now.
 
Uh, thanks?

I'm just a mathematician / scientist who wants us to be accurate. We have a great responsibility to our readership, who can sometimes tend to take rumours to be fact far too quickly. We're still seeing some of that in this thread now.
In your professional opinion, do you think this is not from intel.

QUOTE: Intel's own slides confirm just 2-3 per cent
 

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In my opinion, professional or not, you're reading too much intent into a single line in a single PowerPoint that hasn't been 100% confirmed as the final design. Even if it is the final design (which cooler heads do not yet appear to confirm), it does very little to prove that it was a primary design goal, rather than a consequence.

The facts are in and of themselves interesting. There's no need to project good-and-evil on top of them. Slow down. Let the facts emerge. Analyse them as they come. This thing is not due out for a couple of quarters at the earliest, all sources seem to point to the same 19 bytes on bit-tech. If it's true, other sources (e.g., ars technica) will emerge.
 
Well 3Q 2011 looks better, however expensive.

QUOTE: also mirror what we've heard and go further to include details Intel's upcoming LGA2011 Sandy Bridge-E and 'Patsburg' chipset that will replace the current X58 and LGA1366 platforms.

According to HKEPC the upper limit DDR3 support currently exceeds 2,666MHz (wowzers) and most importantly follows previous current generations basic designs so overclocking potential is unaffected, yet, unspecified
 

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I just found this intresting

QUOTE:According to one Taiwanese motherboard company, on a Sandy Bridge system, the fact that all the busses are linked means that turning up the Base Clock by just 5MHz caused the USB to fail and SATA bus to corrupt.
We chatted about possible work-arounds but at the moment the few 'asynchronous' setups tried were currently not working. It's been claimed to use out-of-the-box the design was deliberately limited with the intention to simplify board design and lower costs. This obviously has the 'unfortunate' side effect that enthusiasts will be unable to manually overclock Sandy Bridge CPUs to their limits, but the CPU's own internal overclocking, TurboBoost, will still work and Intel will offer some controlled multiplier overhead for enthusiasts as a token gesture.

If bit-tech did talk to the Taiwanese and it's true, it does not make any sense, decrease the complexity of the motherboard for cost and increase the complexity of the CPU and PCH

QUOTE:Energy cannot be created or destroyed" this fundamental law of nature, it can only be redistributed or changed from one form to another


That'd be socket 2011, socket 1155 is for cheapskates.
LOL I'm one of those vary vary vary cheapskaters.:rain:
 
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