- Joined
- May 15, 2006
Due to physical modification? Absolutely not.
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Ivy Bridge Delid, Delidding, Delidded
- Thread starter I.M.O.G.
- Start date
- Joined
- Sep 16, 2011
- Location
- Richardson, Texas
No like i have my cpu it dies and they would replace it? I will not change it in anyway.
OP
- Joined
- Nov 12, 2002
- Location
- Rootstown, OH
- Thread Starter
- #24
Yes, the stock processors ran at stock settings are always covered.
If you overclock, you should buy the performance tuning plan to be covered.
Which route you go depends on your conscience, its mostly honor system.
If you overclock, you should buy the performance tuning plan to be covered.
Which route you go depends on your conscience, its mostly honor system.
- Joined
- Aug 5, 2002
I know Opteron 165's were one of them i delidded 2 of them myselftemps went from mid 50's to high 30's under full load
Yup I did that to a few Opteron's as well. Drastic improvement with temps, well worth it.
- Joined
- Sep 16, 2011
- Location
- Richardson, Texas
SO what is you all's opinion about IB vs SB sorry for going off topic, but do you think that i should just jump on a i5-2500k from MC with the $50 off combo or Just wait till IB?
- Joined
- Aug 11, 2008
From delidding, no. If you are at stock clocks and it dies from heat, then yeah. If you want to OC and are worried about heat, then you need to look into getting their Performance Tuning Protection Plan.
EDIT: Left this tab up way too long without refreshing...lol
- Joined
- Jul 29, 2011
- Location
- Buenos Aires, Argentina
You should've got those 200usd 2600k's from MC
There's a week or so for IB launch, you may aswell wait...-let's hope that's true-
There's a week or so for IB launch, you may aswell wait...-let's hope that's true-
- Joined
- Sep 16, 2011
- Location
- Richardson, Texas
lol
- Joined
- Apr 11, 2010
- Location
- London, UK
- Joined
- Feb 16, 2008
- Location
- East Coast
Intels indium solder attach is 80 w/mk conductance, and melts at ~150C, have posted slides in other forums long ago, and perfectly safe to attach solder via intels baking process at high temps, since like previously mentioned cpu isnt on.
I would be shocked if intel was using paste, since paste is going to be no where near 80 w/mK, typcially 10-20x worse than that. Unless intel has a proprietary high conductance non-solder die attach.
But it depends on power density and die attach interface, as to whether it is beneficial to remove the IHS or not, or more importantly if you are going to do direct die cooling the correct way or the clueless way.
All gpus or any cpu that uses paste/non-solder attach typical 3-6W/mK, you could remove the IHS and replace with same crappy user tim 3-6w/mK and do better since removing an equal interface....ie...
gpu die >> crappy paste/die attach 3-6 w/mk conductance >> heatsink1 (IHS) >> user TIM crappy paste 3-6 w/mk, then heatsink 2..... YES, no question it is beneficial to remove one layer of same.
Intel modern cpu I7's however, power density is too high, surface area too small to do direct die with crappy conducting water 0.58 w/mk or crappy user tim 3-6w/mk, unless first spread heat at much faster rate to larger surface area ie like intels solder 20x faster at 80 w/mK ie get surface area much larger before using crappy 3-6 w/mk paste or worse 0.58 w/mk water (same logic behind water blocks needing multiple channels/pins to increase surface area before seeing water). Again, why I doubt intel is using tim paste (certainly nothing we can get ahold of) for TIM1 interface). And if they are, they suck as would ivy temps. But given IVY temps, would be interesting to see what they are using.
silicon die is avg 125 W/mk conductance and nonuniform >> indium-solder attach 80 w/mk (but only 20 microns thick) >> copper IHS 400 w/mK and uniform which significantly increases the surface area before we try to use 4-6w/mK tim paste to transfer again to copper then massive surface area, ie pins on waterblock, before cooling with crappy water at thermal conductance of 0.58 w/mK (air obviously worse).
The worst way to do direct die cooling of modern intel high power density cpus, is remove solder IHS 80w/mk, and then try to directly cool die hot spots with 0.58 w/mk conductance of water with ridiculously low surface area, ie its resistance per unit area, not total resistance. In past, when this argument was at xtreme, published papers showing much more uniform temps across IHS vs die (imaging). Someone on xtreme did delid i7 and directly water cooled and posted his 85C temps on one core at STOCK settings alone. I have pics of delided cpus on xtreme/drilled holes in as well, my temps were worse as well to point cpu was nonusable. Fallwind did water to die, I tried waterblock to die, both utter failure.
The second bad way is to put a waterblock using 4-6w/mk user tim directly on modern die, again trying to spread heat 20x slower than intels indium solder tim. Intel abandoned paste, and spent a small fortune developing the voidless solder attach for a reason.
The smart way to do direct die cooling on modern intel high power density cpu is remove iHS, then resolder the waterblock to the die with 80 w/mk solder at same very thin 20 micron bond thickness....so, for example with 30C gradient from core to IHS, you can eliminate possibly 1/3 or more of the gradient (here, post 13, 22). Because now you have pin point heat areas, but being spread at 80 w/mk to copper waterblock (also now heatspreader) then to high surface area pins in waterblock at 400 w/mk, before using water at 0.58 w/mK...and you eliminate the user die interface 3-6w/mk tim.
At 150w 45nm or smaller intel high power density with very small surface areas, it is futile to attempt to cool that much heat at an incredibly small surface area at rate of either 4-6w/mk or more laughable 0.58 w/mk. That is like cutting off fins on a heatsink to "remove a layer of copper", so air can get directly to base of heatsink.
I have yet to find a single person that has delided an i7 and got better temps. I know of one that made such a claim, never posted proof, then later when questioned changed his story.
But now curious to know what intel is using on these, if not solder.
I would be shocked if intel was using paste, since paste is going to be no where near 80 w/mK, typcially 10-20x worse than that. Unless intel has a proprietary high conductance non-solder die attach.
But it depends on power density and die attach interface, as to whether it is beneficial to remove the IHS or not, or more importantly if you are going to do direct die cooling the correct way or the clueless way.
All gpus or any cpu that uses paste/non-solder attach typical 3-6W/mK, you could remove the IHS and replace with same crappy user tim 3-6w/mK and do better since removing an equal interface....ie...
gpu die >> crappy paste/die attach 3-6 w/mk conductance >> heatsink1 (IHS) >> user TIM crappy paste 3-6 w/mk, then heatsink 2..... YES, no question it is beneficial to remove one layer of same.
Intel modern cpu I7's however, power density is too high, surface area too small to do direct die with crappy conducting water 0.58 w/mk or crappy user tim 3-6w/mk, unless first spread heat at much faster rate to larger surface area ie like intels solder 20x faster at 80 w/mK ie get surface area much larger before using crappy 3-6 w/mk paste or worse 0.58 w/mk water (same logic behind water blocks needing multiple channels/pins to increase surface area before seeing water). Again, why I doubt intel is using tim paste (certainly nothing we can get ahold of) for TIM1 interface). And if they are, they suck as would ivy temps. But given IVY temps, would be interesting to see what they are using.
silicon die is avg 125 W/mk conductance and nonuniform >> indium-solder attach 80 w/mk (but only 20 microns thick) >> copper IHS 400 w/mK and uniform which significantly increases the surface area before we try to use 4-6w/mK tim paste to transfer again to copper then massive surface area, ie pins on waterblock, before cooling with crappy water at thermal conductance of 0.58 w/mK (air obviously worse).
The worst way to do direct die cooling of modern intel high power density cpus, is remove solder IHS 80w/mk, and then try to directly cool die hot spots with 0.58 w/mk conductance of water with ridiculously low surface area, ie its resistance per unit area, not total resistance. In past, when this argument was at xtreme, published papers showing much more uniform temps across IHS vs die (imaging). Someone on xtreme did delid i7 and directly water cooled and posted his 85C temps on one core at STOCK settings alone. I have pics of delided cpus on xtreme/drilled holes in as well, my temps were worse as well to point cpu was nonusable. Fallwind did water to die, I tried waterblock to die, both utter failure.
The second bad way is to put a waterblock using 4-6w/mk user tim directly on modern die, again trying to spread heat 20x slower than intels indium solder tim. Intel abandoned paste, and spent a small fortune developing the voidless solder attach for a reason.
The smart way to do direct die cooling on modern intel high power density cpu is remove iHS, then resolder the waterblock to the die with 80 w/mk solder at same very thin 20 micron bond thickness....so, for example with 30C gradient from core to IHS, you can eliminate possibly 1/3 or more of the gradient (here, post 13, 22). Because now you have pin point heat areas, but being spread at 80 w/mk to copper waterblock (also now heatspreader) then to high surface area pins in waterblock at 400 w/mk, before using water at 0.58 w/mK...and you eliminate the user die interface 3-6w/mk tim.
At 150w 45nm or smaller intel high power density with very small surface areas, it is futile to attempt to cool that much heat at an incredibly small surface area at rate of either 4-6w/mk or more laughable 0.58 w/mk. That is like cutting off fins on a heatsink to "remove a layer of copper", so air can get directly to base of heatsink.
I have yet to find a single person that has delided an i7 and got better temps. I know of one that made such a claim, never posted proof, then later when questioned changed his story.
But now curious to know what intel is using on these, if not solder.
OP
- Joined
- Nov 12, 2002
- Location
- Rootstown, OH
- Thread Starter
- #33
rge: Which water blocks were tried when delidding? The design of direct die waterblocks like the G5 Storm was much different than modern waterblocks designed for use with IHS. I'm asking because I'd like to see this retested, but in best case scenario conditions with a WB designed for cooling a die without an IHS.
In any circumstance, I agree direct water has been proven insufficient, but I do have an inclination that direct WB on die could improve temps considerably if Intel isn't soldering the IHS on with these chips. Nikhsub would take that one step further, and I think he also believes direct WB (if WB designed properly) would always be better than IHS.
Also, do you have the equipment to test it if a donor CPU were provided? (and a g5 storm or similar impingement based direct die WB)
In any circumstance, I agree direct water has been proven insufficient, but I do have an inclination that direct WB on die could improve temps considerably if Intel isn't soldering the IHS on with these chips. Nikhsub would take that one step further, and I think he also believes direct WB (if WB designed properly) would always be better than IHS.
Also, do you have the equipment to test it if a donor CPU were provided? (and a g5 storm or similar impingement based direct die WB)
Last edited:
- Joined
- Oct 12, 2001
- Location
- Los Angeles
I.M.O.G. - direct die cooling is not metal ontop of the die, it is water directly on the die... it is not effective and IDK why it has even been brought up. It will kill the silicone in short order. If we used the indium solder to bond a storm WB to the die, it would cool far better than through the IHS, same goes for a good HSF. I still think a water block designed for bare die (storm, G5 etc) with a user applied TIM would still cool better than soldered IHS and any other water block.
- Joined
- Feb 6, 2011
Does the Intel warranty cover this?
If so, I'd do it.
Of course it is: kill the cpu and "solder" the IHS back with some superglue!
I don't think Intel will take the HIS off for verification...
- Joined
- Feb 16, 2008
- Location
- East Coast
If remove IHS and replace tim1 with an equal or better or maybe slightly worse tim, then no question should get better core temps with direct die, since eliminate 1 layer of equal resistance. And if solder block on, definitely get better temps, remove resistance layer + remove crappy user tim.
And I agree, water block designed for that die would help, and if intel is using non solder attach for IVY, it would be interesting to test. But if replacing 80 w/mk interface with 4-6 w/mk user paste, not interested in testing that one, I know how that will turn out (though granted I have not tested one designed for direct die, but just cant fathom cooling that power density with that low surface area, across relatively high user tim resistance). Though indigo xtreme is now available, 20 w/mk bulk cond with low contact resistance, application is a problem to direct die, but that would be interesting. Thought about trying that before, but again requires a sacrificial mobo/system (just in case), which had 4 yrs ago when testing, but not now.
I have all temp equipment crystalfonz 13 calibrated probes, fluke, IR gun but waterblock on die watercooling requires a mobo/setup your willing to kill, dont have that at the moment, plus the disruptive issue (without separate testing computer) is the cpu socket has to be removed, replace with different mounting mechanism (ghetto made), and try not short anything.
Waterblock I used was swiftech XT, but was 4 yrs ago, cant remember if I had my HK 3.0 then. 2 delided cpus tested, both 45nm core 2 duos, E7200 and E8400 off ebay to replace my e8400 I drilled, also delided e8500 but didnt waterblock test that one. My goal was thermocouple attached to die to see gradient in cpu and across IHS, same reason had drilled ihs on 4-5 cpus earlier, but also had to do direct die cooling to do so, both with water and with air/heatsink. E8400 was soldered and spent most time waterblock testing, E7200 adhesive/die attach, fried both eventually.
Where were you 4 years ago, when I had a separate testing computer all set up. Also regarding sending me to test, you might rethink that after seeing typical result of my before (left pic) vs after testing (right pic/fried die).
And I agree, water block designed for that die would help, and if intel is using non solder attach for IVY, it would be interesting to test. But if replacing 80 w/mk interface with 4-6 w/mk user paste, not interested in testing that one, I know how that will turn out (though granted I have not tested one designed for direct die, but just cant fathom cooling that power density with that low surface area, across relatively high user tim resistance). Though indigo xtreme is now available, 20 w/mk bulk cond with low contact resistance, application is a problem to direct die, but that would be interesting. Thought about trying that before, but again requires a sacrificial mobo/system (just in case), which had 4 yrs ago when testing, but not now.
I have all temp equipment crystalfonz 13 calibrated probes, fluke, IR gun but waterblock on die watercooling requires a mobo/setup your willing to kill, dont have that at the moment, plus the disruptive issue (without separate testing computer) is the cpu socket has to be removed, replace with different mounting mechanism (ghetto made), and try not short anything.
Waterblock I used was swiftech XT, but was 4 yrs ago, cant remember if I had my HK 3.0 then. 2 delided cpus tested, both 45nm core 2 duos, E7200 and E8400 off ebay to replace my e8400 I drilled, also delided e8500 but didnt waterblock test that one. My goal was thermocouple attached to die to see gradient in cpu and across IHS, same reason had drilled ihs on 4-5 cpus earlier, but also had to do direct die cooling to do so, both with water and with air/heatsink. E8400 was soldered and spent most time waterblock testing, E7200 adhesive/die attach, fried both eventually.
Where were you 4 years ago, when I had a separate testing computer all set up
. Also regarding sending me to test, you might rethink that after seeing typical result of my before (left pic) vs after testing (right pic/fried die). Attachments
Last edited:
OP
- Joined
- Nov 12, 2002
- Location
- Rootstown, OH
- Thread Starter
- #38
I know that, I was trying to speak clearly to differentiate a waterblock without the IHS from actual direct die like it was brought up. I should have just said "waterblock without the IHS" instead of "direct die waterblock".
- Joined
- Jul 29, 2011
- Location
- Buenos Aires, Argentina
My goal was thermocouple attached to die to see gradient in cpu and across IHS, same reason had drilled ihs on 4-5 cpus earlier, but also had to do direct die cooling to do so, both with water and with air/heatsink. E8400 was soldered and spent most time waterblock testing, E7200 adhesive/die attach, fried both eventually.
Where were you 4 years ago, when I had a separate testing computer all set up
That reminds me of a new type of TEC's that were being developed...They were TONS more efficient and were intented to use between the die and the IHS or something for specific applications. Can't remember the name though.
- Joined
- Oct 12, 2001
- Location
- Los Angeles
