- Joined
- Nov 3, 2008
Okay, I'll try one last time to explain this. First, you keep confusing the differences in micro-architecture with the actual instruction sets themselves. As I've stated before, there isn't an "SSE2-Intel" or "SSE2-AMD" etc. there is just "SSE2". The instruction sets themselves are standardized and for good reason. Think about how bloated software would be if every time there was a micro-architecture change they had to add code for that specific CPU model. It couldn't ever possibly work. As Hitman tried explaining, an instruction set is just exactly that a set of instructions. How quickly or efficiently the instruction sets are completed is entirely dependent on the micro-architecture NOT the actual instruction sets themselves.
http://en.wikipedia.org/wiki/Instruction_set
I.E. the micro-architecture is changed to run the instruction sets, the instruction sets are not changed to run on the micro-architecture.
I don't know if that's what Aida is doing or not. I just created a "hypothetical" to show how unefficient and restrictive programming for multiple CPU "vendor ID's" would be as well as the inherent problems it would create vs. coding for "instruction sets".
You know I tried to back off of this Bubba and honestly we are talking about two different side of a coin here.
How many virtual processors have you made? It is very relevant to this. I ask you a question or address you and I get Angers blog or wiki. I want you to answer me. I tried to drop out of this part of it you know. We are talking about different things here and you seem to think that if there are registers for an instruction set on a CPU that it is the same implementation as all other CPUs and though the exact same functions may be run the speeds are not the same. This tells us that there is much more to it that just running the code if the CPU says I can run it. Hell the CPU may be faster running as standard int or float than it is using the (insert extension) registers. I really have no idea and evidently you have less of an idea about this than I do.
Like I said we are talking about different things but as to your point I agree that Intel should not intentionally cripple code but I am not talking about that and that is the issue here. It is completely on me; I moved outside of the scope of this thread and for that I am sorry.