PCIE,CPUs,LANES,NVMes AND CHIPSETS?

I seem to have, once again, proven that I know nothing, this time about pcie stuff.
looking at the intel site it would appear that my z97/4790K rigs have 16 pcie "lanes" in the cpu and 8 more "lanes" someplace in the chipset.
I would have thought that they would be someplace buried in the motherboard, like memory traces, what and where are these pcie lanes?
this stems from my failing to figure out that on my asrock Z97extreme9/4790K rigs that I don't have enough of these things to run sli and an NVMe drive.......... sad.........

See diagram....

The z97 chipset only has 16 pcie 3.0 lanes. The chipset/pch supplies 8x pcie 2.0 lanes. The new pcie nvme ssds are pcie 3.0 4x. So in the case of z97, it has to take from the cpu lanes, hence why you can't run sli (but could run amd crossfire x - if your board supports it - because it only needs 4x to run). There aren't any additional 3.0 lanes.

Z170 has pcie 3.0 which come from the pch so it doesn't affect SLI on that chipset as it has more pcie 3.0 lanes to use... with z270 even more.

where are the "lanes"?
are they just the "pipes that connect the gpu to the cpu?

Simply.... yes. There are traces that go from the pcie slots to the cpu via traces on the pcb.

Not as simple: http://www.hardwaresecrets.com/everything-you-need-to-know-about-the-pci-express/

I think I saw in the pictures from ces, an am4 board with 3 m.2 pcie connectors and sli/xfire capable.
what would the lane configuration be for that? 32 lanes to the cpu and 12 to the chipset?

I was under the impression that the new AMD CPUs only have 20 PCIe lanes to share with the PCIe slots, similar to the 6700K iirc. But the board you saw might actually share bandwidth on all 3 of those lanes, I'm guessing there. I woudl think it's a safe bet though, as I don't know of many programs (for the retail market) that could utilize the full bandwidth of PCIe x4.

Which probably means for them to say it's SLI/Xfire capable, GPU run at x8 each and the NVMe would share bandwidth, as they aren't out and I haven't read any manuals on those board's this is just speculation. Again there might be a dedicated lane on the MB that would transfer data from the NVMe slots to the CPU in another fashion, but no clue how that works, that's just way above my understanding.

doing some searching, the ryzen platform will have a total of 24 pcie lanes so we would be able to go sli at x16/x8 or 1 NVMe and single card.
what I thought I saw must have been 1 pcie and the others sata.

The confuguration will vary by board as it does with Intel.

I would have thought that the number of lanes and distribution of lanes would be fixed by the cpu and chipset and the motherboard would be designed around those.
can the motherboard have and use more lanes than those in the chipset and cpu?

caddi daddi said:

I would have thought that the number of lanes and distribution of lanes would be fixed by the cpu and chipset and the motherboard would be designed around those.
can the motherboard have and use more lanes than those in the chipset and cpu?

Click to expand...

If you look at the diagram above Direct Media Interface (DMI) 3.0 from the CPU connects to the Chipset, that is the Platform Controller Hub (PCH). So all you have to do is change the PCH to something different to allow more PCI-E lanes for the Chipset, then that connects to DMI 3.0, then that connects to the CPU.

then is pcie a hardware thingy or software thingy?
can I think of the chipset as a sort of cpu, that I can't do anything with? if it can change the function of the dmi 3.0 connection it must have coding in it.

PCI-E is hardware. The chipset is collection of integrated circuits that control digital traffic on the motherboard, then send the digital data traffic to the DMI 3.0 bus that travels to the CPU. The DMI 3.0 (Direct Media Interface) is a digital signal with multiple lanes.

DMI shares many characteristics with PCI Express, using multiple lanes and differential signaling to form a point-to-point link. https://en.wikipedia.org/wiki/Direct_Media_Interface

Click to expand...