P2B-D Tualatin Build

A recent search brought me to the timeless running Tualatin on CuMine MB w/o Powerleap thread and I decided it was time to dig up some of my classic hardware and show some of the newer members what overclocking was like last century.

But first a bit of history:

Back when companies like Asus and Abit would defy intel and build boards to run CPUs in all sorts of unsupported configurations, when FSB or Vcore changes were made by jumpers or soldering iron, when motherboard manuals were so badly translated they were hilariously frustrating to read, when there were only 12 different types of Lego pieces, and yes, when you had to walk 20 miles to school each day - uphill both ways...

The 16bit 8086 (1978) gave birth to the x86 architecture. The 8088 was a more cost effective variant with an 8bit external bus. If you needed hardware floating point capability (ie: for AutoCad) you'd have to add the 8087 coprocessor.

As a tribute to the 8086, Intel's PCI Vendor ID is 8086.

The 80186 was used mainly for embedded applications.

The 286 (1982) improved the 8086.

The 32bit 386 (1985) was a huge leap in performance and features, and allowed you to multitask using Windows 3.1.

The 486 (1989) integrated the floating point coprocessor into the CPU resulting in a huge increase in floating point ops. AutoCAD users wept with joy.

The P5 / Pentium (1993) continued the evolution of the x86 family adding the capability to execute more then one instruction per clock, and eventually introduced the MMX instruction set. These CPUs were paired with 430 series chipsets.

Which brings us to the age where this build originates - the P6 era. The P6 family originated in 1995 and lasted until Netburst made it's debut in 2000. Due to its high efficiency in 2003 an enhanced version of the P6 architecture was revived as the "Core" series (Pentium M) which was eventually succeeded by the 64bit "Core 2" series in 2006.

The first P6 CPU was the Pentium Pro (1995). One of the main features was the on-package L2 cache which was connected via a BSB (Back Side Bus) and ran at full CPU speed. Because this on-package L2 arrangement was difficult to manufacture yields were low and the cost of the Pentium Pro CPUs was high.

Unable to bring on-package L2 yields under control, in 1997 the Pentium II was introduced on a Single Edge Contact Cartridge (SECC) daughterboard which contained both the CPU and separate L2 cache chips. In a further effort to reduce costs the L2 cache on the Pentium II only runs at half the CPU speed.

Celerons were introduced in 1998, which at first were PIIs with no L2 cache at all. These were so slow that they were quickly replaced by Celerons with 128kb of L2 cache as intel began to experiment with adding L2 cache directly on the CPU die.

In 1999 intel released the first PIII (Katmai) on the 250nm process at speeds from 450-600mhz (100/133mhz FSB). Like the PII, it continued to use separate L2 cache chips running at half the CPU speed. Overclocks were often limited by the speed of the L2 cache chips and not the CPUs themselves

By 2000 intel had mastered the technique of on-die L2 cache and introduced the 180nm Coppermine PIIIs at speeds from 500-1130mhz (100/133mhz FSB) which contained 256kb on full speed on-die L2 cache. With the L2 cache now on-die intel began to migrate back to a socketed design for CPUs, although Coppermine PIIIs were available in both slot and socket 370 form. Celerons continued to be available with 128kb of L2 with a 100mhz FSB.

In 2001 intel made a further die shrink to 130nm and released the Tualatin based PIII cores at speeds from 1000-1400mhz in s370 form only - the die shrink not only resulted in a lower Vcore but a GTL bus voltage drop from 1.50v to 1.25v. There were three Tualatin versions available:
PIII-S with 512kb L2 and 133FSB, SMP (Symmetric MultiProcessing) enabled
PIII with 256kb L2 and 133FSB
Celeron with 128kb L2 and 100FSB.

Celerons were popular with overclockers as they were cheap and had high multipliers.

The early P6 cores used 440/450 series chipsets (the 450 being more server oriented). The 810/820/840 series chipsets debuted with the Coppermine cores, and were the only chipsets to officially support the Tualatin cores due to the lower bus voltage.

The 440BX chipset was often considered the best P6 overclocking chipset as it supported more SDRAM memory and could overclock to the same speeds as the later 815 series. It was also generally faster at the same FSB. On the flip side 440BX only supported AGP 1.0 (2x), ATA-33, and had fewer USB ports.

I will be using my 440BX based Asus P2B-D for this build which I bought over 16 years ago. It is revision 1.06 D03 which was the last hardware version made. The un-populated section is for the SCSI option available on the P2B-DS.

As Coppermine s370 processors quickly became the norm, various companies started to make "slockets" which would allow people to run s370 CPUs in their existing Slot 1 boards. Motherboard manufacturers such as Abit, Asus, and MSI produced various slockets, as did specialty companies such as PowerLeap and Upgradeware.

The type of board and processor you wanted to run determined what kind of slocket you need. Earlier 440 series boards only had voltage regulators that went down to ~1.8v while later boards would go down to ~1.3v. Coppermines will generally tolerate 1.8v Vcore indefinitely but not Tualatins. While some slockets just map the s370 pins to the appropriate Slot 1 contacts, others include voltage regulators to provide the 1.4v~1.5v vCore Tualatins require when used on boards that only go down to 1.8v. Tualatin compatible slockets also remap a few pins that intel changed to stop Tualatins from booting with chipsets that don't support the 1.25v GTL bus, although you can also do this yourself. Some slockets supported SMP natively, but again you can mod many of them if not.

Basically, a slocket provides a cheap piece of hardware between a s370 CPU and the chipset that allows for easy hardware modifications to run combinations of hardware never supported by intel.

I have a pair of Upgradeware Slot-T rev 1.1 slockets that support both Tualatins and SMP which I had been previously using in other Slot 1 boards for this build.



They are equipped with Texas Instruments TVC16222A 22bit voltage clamps (datasheet: View attachment TI TVC16222A.pdf) to reduce the some of the basic I/O signals from the 2.5v Slot 1 boards use to the 1.5v that s370 CPUs expect.



As my 440BX board is a later revision it has an intersil HIP6019BCB voltage regulator (datasheet: View attachment intersil HIP6019B.pdf) that goes down to 1.3v located between the two CPU slots...



... and an ICS 9250CF-08 frequency generator (datasheet: View attachment ICS 9250CF-08.pdf) that allow for FSB selection between 66mhz and 150mhz located between CPU slot #2 and the memory slots.

Even though my board has the newer ICS 9250CF-08 frequency generator it still only has three FSB selector jumpers (FS0, FS1, FS2) which means that only options in the lower half of the chart (where FS3 = 0) can currently be selected. There is a 133FSB option in the lower half [0,1,1,0] but that would overclock the PCI bus to over 44mhz which is not ideal. What we really want is access to the top half of the chart (where FS3 = 1) which would not only give us 133FSB with a 33mhz PCI bus but also the option of 140FSB or even 150FSB.



A quick look at the pinout from the datasheet shows that our missing FS3 shares pin #9 with a PCI clock signal.



The datasheet also tells us:

Shared Pin Operation - Input/Output Pins

The I/O pins designated by (input/output) on the ICS9250-08 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads.

To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm(10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period.

So what we need is a way to toggle pin #9 to VDD or GND through a 10k resistor. A quick order from DigiKey yields a 12 position (4x3) header block and a 10k 1% 1/10W resistor (same specs as the 0603 SMD resistors on the board).



The pins (legs) on the ICS9250-08 are a little too close together for my soldering skills so I'm going to aim for the pin side of the SMD resistor.



An old floppy or PATA cable keeps the pins on the header block straight when soldering, and makes it easier to hold.



I pre-tinned the original 3x3 header block pins before soldering the new 4x3 header block onto it, with the extra row overhanging on the side closest to the ICS9250-08. The middle pin was tricky to get to - I ended removing the two outboard SECC support towers. I have a Weller WESD51 soldering iron and used an ETR tip @350C.



Next I soldered the two new outboard FS3 pins to the corresponding outboard FS0 pins (which ring out to VDD and GND) using the legs off another scrap resistor.

I then laid out my 10k resistor and cut it to length, keeping the actual resistor as close to the ICS9250-08 as possible. I slipped some heatshrink tube over it and soldered one end to the new middle FS3 pin. After inducing some final bends into the 10k resistor so that it was hovering directly above where it was going to attach (and tinning the end), I heated the resistor lead a few mm above the SMD pad while pressing gently down. After about one second the solder on the SMD pad melted and enveloped the end of the resistor lead.



So now I have an FS3 jumper, and they are all a bit higher which makes them easier to reach. The only thing to remember is that they are out of order - FS3, FS0, FS1, FS2.



Testing will have to wait for tomorrow. I'll try and find my heat gun to shrink that heat tube as well.

I've got four 256MB sticks of Crucial (Micron) PC133 CL2 that use Micron 48LC16M8A2 memory chips. These are low density sticks which are required for the 440BX (the GX was the only 440 series chipset to support high density memory). From previous experience on other boards I know they will all do 133 CL2 and 150 CL3 without issues.



For testing purposes I have a Tualatin based Celeron-1000 (because it's an easy 10x mulitplier) in the 2nd CPU slot (via an Upgradeware Slot-T jumpered for 1.5 Vcore) and terminator card in the 1st CPU slot. Plus a Radeon 8500LE in the AGP slot.

Testing our new jumper settings shows that the board will boot fine at 124FSB with all four memory modules.



At 150FSB it will only boot with one memory module.



Further testing shows that 133FSB is the current maximum for three modules, and 140FSB for two.

Also, the 8500LE outputs in black and white (greyscale) at 150FSB, as per the above screenshot. This is most likely because while the default AGP speed is 66mhz, the 440BX only has 1/1 and 2/3 AGP multipliers so at 150FSB the AGP bus is running at 150x2/3= 100mhz.

I had to spend some time and deal with a leaking kitchen window, and when I got back to this project the board would not boot. All components worked fine in my P3B-F so it kind of narrowed it down to the BIOS - it must have become corrupted when I had the board up at 150FSB (50% overclock).

After monkeying around for a week trying to find both a 1.44MB floppy drive and disk that worked I ended up spending $20 on a new BIOS chip from ebay. My original thought was to hotflash the original BIOS chip using the P3B-F but I figured I'd just get a spare BIOS chip since I'd be doing some BIOS modifications later and it might come in handy. Eventually a friend loaned me a few 1.44MB floppies and I was able to hotflash the original BIOS so now I have two working BIOS chips.

And I got three SL6BY chips off ebay as well.



Next on the list is to get the board to post at higher FSB with all four memory slots populated. With three memory modules installed and running at 133mhz CL2 the memory voltage can be measured at pins 1 and 6 on the 4th (empty) memory slot - it's possible but much harder to measure on a populated slot.





3.204v is a fair bit below the 3.3v that the modules are rated at.

I believe the first place the Vio mod was written up was here and he (she?) initially started with 3.22v, so not that different then me.

A read through the HIP6019BCB voltage regulator Application Note 9800 (View attachment intersil AN9800.pdf) tells us that the Vio voltage = 1.265 x ( 1 + ( ( R3 + R5 ) / R6 ) ).

Following the traces from the HIP6019BCB on the board tells us that R3 [R56] = "67B" = 4.87k, R5 [R48] = "50B" = 3.24k, and R6 [R50] = "69B" = 5.11k



*** Note: the resistor values on this diagram are suggested values only - not what exists on the P2B-D board ***



So currently Vio is resistor programmed for:
volts = 1.265 x ( 1 + ( ( 4.87 + 3.24 ) / 5.11 ) )
volts = 3.273

3.204 / 3.273 = 97.9%, or a 2.1% droop.

Aiming for a memory voltage of ~3.35v at the slots and allowing for the same droop, we want to program for 3.350 / 0.979 = 3.422v

R5 ([R48] on the board) is probably the best resistor to replace as it is on the feedback pin (and easy to get to), so its new value should be:
3.422 = 1.265 x ( 1 + ( ( 4.87 + R5 [R48] ) / 5.11 ) )
R5 [R48] = 3.843k

The closest standard resistor is 3.83k which will give us a theoretical:
volts = 1.265 x ( 1 + ( ( 4.87 + 3.83 ) / 5.11 ) )
volts = 3.419

So using a 3.83k resistor in R5 [R48] and allowing for the same 2.1% droop should result in approximately 3.419 x 0.979 = 3.347v at the memory slots.

The other voltage modification to be worked out tomorrow is reducing the GTL bus voltage - Tualatin CPUs use a lower GTL bus voltage (1.25v vs the 1.5v older processors use) as described in the first post. This page goes into more detail on this mod

According to the application note the GTL bus voltage (Vtt) = 1.265 x ( 1 + ( R11 / R12 ).

Following the traces from the HIP6019BCB on the board tells us that R11 [R62] = "29B" = 1.96k, R12 [R63] = "103" = 10k

So currently Vtt is resistor programmed for:
volts = 1.265 x ( 1 + ( 1.96 / 10 ) )
volts = 1.513



Measuring the voltage from the far side of R11 [R62] to GND gives us 1.502v.



1.502 / 1.513 = 99.3%, or a 0.7% droop.

Aiming for a GTL bus voltage of ~1.36375v (halfway between the minimum Vtt of 1.365v for AGTL+and a maximum Vtt of 1.3625v for AGTL as explained on this page) and allowing for the same droop, we want to program for 1.3625 / 0.993 = 1.372v

Therefor the new value for R11 [R62] should be:
1.372 = 1.265 x ( 1 + ( ( R11 [R62] ) / 10 ) )
R11 [R62] = 0.846k

The closest standard resistor is 0.845k which will give us a theoretical:
volts = 1.265 x ( 1 + ( 0.845 / 10 ) )
volts = 1.372

So using a 0.845k resistor in R11 [R62] and allowing for the same 0.7% droop should result in approximately 1.372 x 0.993 = 1.362v. As this is a little below the ~1.364 we can try the next size up.

The next size up resistor is 0.866k which will give us a theoretical:
volts = 1.265 x ( 1 + ( 0.866 / 10 ) )
volts = 1.375

Allowing for the same 0.7% droop a 0.866k resistor should result in approximately 1.375 x 0.993 = 1.365v - I don't think the ~0.003v would really make any difference but 1.365v just looks like a nicer number.

I was using an old Thermaltake Volcano 7 for testing the board with one CPU, and ended up ordering a Volcano 11 off ebay for the other. The Volcano 7 (currently on the slocket closest to the memory) looks to be the better heatsink as it is skived, whereas the fins on the 11 are glued on with thermal glue.



Look ma, 2 Processor(s) Detected!



The CPUs have x10.5 multipliers and board is running at 100FSB (until the Vio mod is complete) so 100FSB x10.5 = ~1050mhz.

I ordered the new SMD resistors for the voltage regulator - 866 ohms and 3.83k ohms. There was a price break at 10 so I splurged and spent a grand total of $1.18 for 20 resistors (10 of each).



Once upon a time I might have tried to solder 0603 size SMD resistors, but since I know a place with all the right equipment that'll do it for $20 I'm going to chicken out. They are really small.

Subbed, and you should meet these guys. LOL http://www.overclockers.com/forums/showthread.php/782242-History-of-overclocking

man when you talk about dual cpus with s370 first board that comes to mind is the Abit BP6, which you can still find on ebay from time to time. im glad you posted pics of the ram, one guy here was teling me there was no CL listed for SD ram. i have 256mb PC133 CL2 sticks from micron, which reminds me i know i got one on my desk somewhere, need to look through the parts bin.

Subbed.

o JC have you replaced the caps in the power supply section for the cpu and other areas? just a way of saying keep an eye out for bulging caps, biggest sigh they need to be replaced.

Caps all look good on this board - I don't think I've had any problems on my Asus P2B/P3B boards. Recently I re-capped my WRT54G (https://arstechnica.com/information...r-from-2005-still-makes-millions-for-linksys/).

So I got the programming resistors for the voltage regulator swapped out yesterday:



New Vio (old was 3.204v):



New Vtt (old was 1.502v):



Vio is off by less than 1%, and Vtt is exactly what I was looking for.

This is by far one of the most interesting things I've seen on here in YEARS. Please post an update!! I have a P2B-DS (same board, but /w SCSI) and two PIII 733s up in the shed... can't wait to play with it more in the near future. May water cool it and add VooDoo II SLI... or my V5 5500.