[JimmyG]

There are IDE, EIDE, SCSI, SAS, and SATA interfaces in use.

To me, a parallel interface such as IDE, and EIDE have the advantage of sending all data bits in parallel. This gives this interface a speed advantage over serial interfaces such as SCSI, SAS and SATA interfaces.

However, parallel interfaces seem to have gone out of favor and I don't know why. I can think of a couple of possible reasons but I am unsure what the limitations are:

Parallel advantages:
1. All data arrives in parallel one word at a time for fast data transfer.
Parallel disadvantages:
1. Cable lengths are limited.
2. Cables are bulky.

Serial advantages:
1. Small cables.
2. Better cable lengths allowed.
Serial disadvantages:
1. Data arrives one bit at a time so a 64 bit data word takes 64 times longer to be transmitted over the cable.

I'm sure some of my assumptions above will be called into question. That's why I'm starting this thread: to find out the real story....so fire away!

[MattNo5ss]

PATA interfaces are slow compared to the other interfaces.

• IDE does ~133-167MB/s or so
• SCSI can do up to 5Gb/s (640MB/s theoretical)
• SAS and SATA can do 6Gb/s (768MB/s theoretical)

Also, I think IDE is limited to smaller HDDs b/c of its lower LBA.

[Techjesse]

Serial ATA was designed to replace the older parallel ATA (PATA) standard (often called by the old name IDE), offering several advantages over the older interface: reduced cable size and cost (7 conductors instead of 40), native hot swapping, faster data transfer through higher signalling rates, and more efficient transfer through an (optional) I/O queuing protocol.
SATA host-adapters and devices communicate via a high-speed serial cable over two pairs of conductors. In contrast, parallel ATA (the redesignation for the legacy ATA specifications) used a 16-bit wide data bus with many additional support and control signals, all operating at much lower frequency. To ensure backward compatibility with legacy ATA software and applications, SATA uses the same basic ATA and ATAPI command-set as legacy ATA devices. Here's what to look for in the future:
The current move to the SATA 6Gb/s interface standard is a temporary stop-gap system while the SATA-IO working group refines its SATA Express standard. Designed to combine the software infrastructure of SATA connectivity with the electrical transfer interface of PCI Express, the SATA Express standard promises peak transfer rates of up to 16Gb/s compared to the 6Gb/s offered by standard SATA. (Note: that's 2GB/s) http://www.bit-tech.net/news/hardwar...sata-express/1

[Neuromancer]

SATA 6Gbps I am pretty sure is limited to about 560 MBps in reality.

Nice read jesse, thanks

Although if 16Gbps is true that will boil down to 1.4 GBps actual maximum

[Techjesse]

How about this String 24 SSDs together for 6TB & 2GB/s throughput
http://blog.tmcnet.com/blog/tom-keat...throughput.asp

[petteyg359]

@OP: See https://en.wikipedia.org/wiki/Serial...ersus_parallel

[WarDad]

Think of parallel as a parade of soldiers marching. Each line must cross the intersection together. If you make them jog or run they will break ranks and scramble the data.
Now think of serial as a single line of fast horses.

At one time I was lab testing new Video DACs that had a 10 Bit 200MHz+ data bus. The HP Data generator was limited to 200MHz, but could be pushed to 240MHz+. I opened one of their data pods (differential input) for 3v High Speed CMOS output and saw the typical bus buffer chips and a lot of squigly traces. They were matching trace lengths to match the delays for all of the data bits. I did the same for my evaluation boards and added some nominal terminations to reduce reflection interference. I did manage to get 245MHz, but I could put the clock any where I wanted it, and there was one sweet spot only 0.1ns wide. I did this with very basic PCB schematic capture and layout sotware and a cheap web based PCB build house.
The clock is like the intersection line in the analogy I started out with.
It's not just about matching printed circuit board trace lengths. It's about matching the impedance and parasitic losses. A capacitor is two conductors serperated by an insulator. A PCB trace is copper (conductor) seperated from a ground plane (conductor) or other conductors by the FR4 fiberglass (insulator), so it has some parasitic capacitance. Current moving thru a conductor bulds a magnetic field, so all conductors are inductors. So now your dealing with LCR transmission lines and the parasitics can be difficult to control, and you need 8 or more identical sets. It just keeps spiraling in complexity.