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Old 04-24-12, 01:56 PM   #121
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Old 04-24-12, 02:40 PM   #122
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Hmm, sounds like another Prescott. Harder to dissipate the heat, for not much gain.
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Old 04-24-12, 02:51 PM   #123
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Quote:
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LOL !! Secret sauce = TIM as far as im concerned..
Most likely a material like diamond dust or other non capacitive/inductive matrix.
As long as it equals or exceeds solder's thermal conductivity. There had to be a good technical reason for Intel to abandon soldered IHS, not just a few pennies per/cost savings. Maybe soldering the IB drastically reduces final yields due to the thermal stress of the soldering process on the tri-gate 22nm denser structure.

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Old 04-24-12, 03:01 PM   #124
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I wonder if the $25 intel insurance would cover the lid "popping off" by "itself"

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Old 04-24-12, 03:39 PM   #125
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I wonder if the $25 intel insurance would cover the lid "popping off" by "itself"
unlikely since that is physical damage

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Old 04-24-12, 03:46 PM   #126
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Maybe if the IHS was disloged while applying the intel HSF while following Intel instructions?


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Old 04-24-12, 03:48 PM   #127
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Sauce definitely implies a liquid of some sort, not many people will say sauce about solder :P

Given the slab of copper over the top I seriously doubt conductivity/inductivity/capacitivity matters much

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Old 04-24-12, 03:49 PM   #128
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Its the only barrier left... delid to confirm what is causing/influencing the thermal buildup.. If it makes little difference, then it is because of the chip's density. But if it makes a very big difference, then Intel has some adjustments to make..

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Old 04-24-12, 03:52 PM   #129
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FWIW in the context it was given to me, the literal translation of "secret sauce" would be "we aren't going to tell you". It wasn't meant to actually imply anything about the nature of the interface material. I might have caused a little confusion with my humor in the previous post.

Personally, I have little grounds to believe anything, but I believe they haven't used solder on Ivy Bridge where we are seeing high temps... With a delid to eliminate the extra heat interface and the IHS barrier, and some modification to the socket area to allow good direct contact with the die, I think temps would be a lot better, like in the 15-20C better range.

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Old 04-24-12, 03:55 PM   #130
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Has anyone checked the flatness of the IHS yet? People use to be obsessed with that.. havent seen a comment about it yet.. Its a pretty easy measurement..

Anybody want to lap one?

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Old 04-24-12, 03:56 PM   #131
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Intel's new TIM:



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Old 04-24-12, 04:00 PM   #132
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Quote:
Originally Posted by diaz View Post
Has anyone checked the flatness of the IHS yet? People use to be obsessed with that.. havent seen a comment about it yet.. Its a pretty easy measurement..

Anybody want to lap one?
Or rest a known flat surface across it (razor blade). I think some waterblocks and regular heatsinks are already bowed slightly anyway? Not certain.

Still worth it to find out!

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Old 04-24-12, 04:30 PM   #133
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Quote:
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Intel's new TIM:


Silly me. I thought it was Aloe Vera and cold beer........always makes the heat go away at the beach.

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Old 04-24-12, 05:17 PM   #134
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I don't believe it's power density intel knows what the doing when it comes to die shrinks

QUOTE:You can also increase a chipís dynamic power density by cramming more transistors into the same amount of surface area.
LINK: http://arstechnica.com/old/content/2007/01/8716.ars

However there is 47.3% more surface area with 22nm compared to SB so there is no cramming involved.

Mater of fact intel had so much surface area they shrunk the die from 216 mm≤ to 160 mm≤ and they are able to keep the same density because there is 47.3% more surface are switching to 22nm

IB runs cooler also has lower power use at stock compared to SB

Comparing Prescott scaled only a measly 12% beyond Northwood, which was attributed to the very high power consumption and heat output of the processor. LINK:http://en.wikipedia.org/wiki/Pentium_4

So the die shrink was not the problem with prescott either.

So that leaves the new TRI gate transistor.
Here is intels PDF on tri gate it's what I feel gets it hot overclocking.
QUOTE:Inversion layer area increased for higher drive current LINK:http://download.intel.com/newsroom/k...esentation.pdf

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Old 04-24-12, 05:29 PM   #135
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Quote:
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I don't believe it's power density intel knows what the doing when it comes to die shrinks

QUOTE:You can also increase a chipís dynamic power density by cramming more transistors into the same amount of surface area.
LINK: http://arstechnica.com/old/content/2007/01/8716.ars

However there is 47.3% more surface area with 22nm compared to SB so there is no cramming involved.

Mater of fact intel had so much surface area they shrunk the die from 216 mm≤ to 160 mm≤ and they are able to keep the same density because there is 47.3% more surface are switching to 22nm

Smaller die = less surface area. The die size is a measure of surface area.
They aren't talking about the amount of space a transistor takes up, they're talking about how many transistors are in a given die size.

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Old 04-24-12, 05:32 PM   #136
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Quote:
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Thats incorrect IB at 4.8GHz oc is 277 watts load and stock it's 134W load. My SB at 4.8GHz is 233 watts.
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Well, the problem is you are comparing two different systems... mobo's, ram, hdd, etc. So though it may not make up the difference, its tough to compare non like systems and come to a conclusion. That and, he mentioned stock you go to overclocked to prove your point... LOL!
Yes i know it's not the same system to compare, I was just showing diaz load overclocking watts on IB and my SB also ldle watts on IB so he will know how hot it can get.

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incorrect.. It is only hotter at the core where the temps are taken. The heatsink only has to deal with 77watts vs the 95 of SB for example. The heatsink should still be quite cool to the touch on most occasions with IB.
However since you brought up overclocking watts SB vs IB i wll be doing that when i purchase a IB.

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Old 04-24-12, 06:05 PM   #137
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Quote:
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Smaller die = less surface area. The die size is a measure of surface area.
They aren't talking about the amount of space a transistor takes up, they're talking about how many transistors are in a given die size.
Yes i agree and when you shrink to 22 nm you can fit more in the same space without cramming transistors, so the power density stays the same.

intel does not pack more transistors in the same space, there shrunk so you can fit more and they reduced the die size also some times because they have more surface area than needed, intel knows what there doing when it comes to transistor and tracers shrinking.

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Old 04-24-12, 07:15 PM   #138
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No, the power density goes up. 95w in 200sq mm is a higher power density than 95w in 250sq mm, for example.
Same power, smaller space, more power density.

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Old 04-24-12, 07:24 PM   #139
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TDP is 77W for IB bobnova. 95W is marked on the boxes so that board manufacturers design to the 95W spec for Z77, otherwise they could design for 77W TDP, and then you'd have Z77 boards that weren't fully compatible with Sandy Bridge.

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Old 04-24-12, 08:24 PM   #140
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Did we get confirmation of that from Intel, or is that just based off one third party site?

Even with a 77W TDP you get the following:
SB has 0.43981 watts per square mm.
IB has 0.48125 watts per square mm.

So power density did go up, even with a 77w TDP.

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