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Frankly, the headline and summary are over the top. Where's the quality control? At best, this is editorialising.
Deliberately restricting overclocking? Are you really sure that the sole and only reason Intel is reducing down to a single on-die clock generator is to thwart overclocking? Not to, say, simplify design and reduce cost? Because these seem like logical things to do, trending along with on-die memory controllers and the like.
In fact, the linked bit-tech article says as much, albeit in a breathless manner that assumes intention where I'd imagine there is none. This seems to be deliberately limiting overclocking in the sense that gravity deliberately interferes with my dreams of flying like superman.
I think we could have done a better job of objectively decoupling the editorialising (assuming certain dastardly intentions) from the reporting (the chips will do X). We're better than this.
It's certainly not the end of the day. "Normal" users get a cheaper chip, more of the system is on the chip (with presumably fewer failure modes as a result), and the rest of us can happily bypass the clock signals onboard. Big deal.
More accurate headline: Sandbridge on-die clock generator will likely break current overclocking methods.
I don't think it's going to be fun if Intel sets there engineers to make a chip that we can't overclockwe'll have to work a lot harder to get those good overclocks. But that's the fun
I betcha the DMI bus clock signal is the clock signal, it'd make sense given that the DMI is a PCIe bus with a new name.
I was talking to someone (ghost?) about the very first SB chip seen in the wild and how it looked like they were using PCIe directly for the bclk and how it'd be a major pain to OC. Wish i'd posted that convo back then, i'd look like an oracle or something now
Wikipedia as linked by wingman99 said:It provides for a 10Gb/s bidirectional data rate. It was first used with the ICH6, released in 2004. It is a (perhaps modified) PCI-E x4 v1.1 interface.
I totally agree until Intel puts the PCH and CPU,IMC on a single Chip for the sake of speed improvement.As James Bolivar DiGriz says: What man can lock and encode man can unlock and decode
I betcha the DMI bus clock signal is the clock signal, it'd make sense given that the DMI is a PCIe bus with a new name.
Like i said:
The current DMI is a 4x PCIe 2.0 link, which totals 2GB/s.
http://www.bit-tech.net/hardware/cpus/2010/04/21/intel-sandy-bridge-details-of-the-next-gen/1
Gotta keep in mind, a PCIe 16x 2.0 slot is a whopping 8GB/s of bandwidth.
OK, who the hell are you? Did you, in a past profession, have experience as a writer/editor?
I only ask because what you just said makes perfect sense and is an example of a much larger problem in all outlets of media/journalism (especially politics) and is something I think we should all be more cognizant of.
Thus, I would like to subscribe to your newsletter.
(edit*** Also, I forgot to add: in my experience, what you said usually comes from the mouth of a crazy old dude with tautologically infallible conspiracy theories about 9/11 and etc. Even if they're right... I mean... they're crazy. Surprisingly, your rant was quite reasonable.)
In your professional opinion, do you think this is not from intel.Uh, thanks?
I'm just a mathematician / scientist who wants us to be accurate. We have a great responsibility to our readership, who can sometimes tend to take rumours to be fact far too quickly. We're still seeing some of that in this thread now.
LOL I'm one of those vary vary vary cheapskaters.That'd be socket 2011, socket 1155 is for cheapskates.