Tipycol said:
Is there any way an average guy can do this mod? I wouldn't mind having a locked pci/agp bus now instead of waiting for an nForce 2 
Thanks
Tipycol
Sure. But when you say average, I'm not sure just how 'average your talkin'
!?
To modify the mechanics of the PLL's operation requires good de-soldering skills for starters. I'll try to give you a simplified overview as to how the PLL works, and what needs to be modified.
The basic function of a PLL or also called "clock synthesizer" is to produce an electrical pulse as an output, which is used in keeping the entire system's busses in time or in rhythm together and each at their respective frequency. The PLL has to reference it's output frequencies from somewhere also. The PLL's reference freq. come from the Clock Crystal, which is at a pre-defined frequency. It's at a pre-defined frequency because of physics. The Clock Crystal is just that: Quartz Crystal. Whenever a certain amount of voltage is applied to Quartz, it vibrates at a certain rate or frequency. Some watches and clocks keep their time this way, because it's very accurate.
So let's do a quick review:
The clock crystal produces a frequency for reference. The PLL uses this reference so it knows what to base it's output frequencies on. The PLL will only divide or multiply the clock crystal's frequency according to what it's output(s) need, and according to the way the PLL's been programmed for.
They only have a certain amount of programmed divisors or multipliers.
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EXAMPLE: (The PCI output has been programmed in the PLL to stay at 33 MHz)
If FSB = 100 MHz
then PCI = /3 (or 1/3 divisor to keep it at 33.33 MHz)
If FSB = 133 MHz
then PCI = /4 (or 1/4 divisor to keep it at 33 MHz)
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There is sometimes two PLL's onboard:
1) One of them does RAM, and
2) the other operates the FSB, AGP, & PCI.
We'll focus on #2.
Ok, now you may already be following what I'll soon be getting at..so I'll ask this question:
(Q.) What would happen if we replaced the clock crystal with another of a higher frequency value?
(A.) You essentially 'lie' to the PLL, so it's actual output frequencies will be higher than it would have with the original clock crystal.
This can be both good and bad.
Good, because your squeezing more of an overclock from your FSB.
Bad because some busses other than the FSB, will be too overdriven. Especially the time(hour becomes less than 60min), the PCI bus becomes out of spec, as well as the AGP. This leads to instability...
(Q.) So, how do you stop the other busses from becoming overdriven?
(A.) You intercept their input lines where they leave the original PLL, and wire them into your own PLL circuit you made on another circuit board complete with the original Clock Crystal you removed earlier.
So now you have the capabilty of having a set frequency for the PCI & AGP bus regardless of the FSB setting.
I do realize I haven't given a thorough overview (for the sake of time), and that in parts it may seem sketchy & hard to follow, but I'll try to update this with better explanations and examples....or pictures if I can find a host....
-PC
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