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Taking a P4 beyond the dreaded 1.75V

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penguinpoo

Member
Joined
Sep 17, 2002
Im considering taking a 2.4B 2.4 beyond 1.75V ... after trying out 183FSB.... at 1.65V it would be a bit error ridden, however i tried it at 1.7V and it was better, but still went back to desktop when running 3D mark... I was thinking of taking it to 1.8V, ive read the S.N.D.S Thread... and wanted to ask users there thoughts on taking the 2.4B over 1.75V

As it does 169FSB perfectly stable, at stock core [3.02GHz] but after 169 it goes strange.
 
i dont really have anything to say about the SNDS...
but you can go to higher vcore if you want to...
not sure if its a good idea to run it everyday...
but on the safe side i wont recommend it...
i keep my vcore to 1.7max when i overclock...
 
I say stop while your ahead. I would highly recommend not going above 1.70V actual with the NW CPUs. This being the device physics involved in 0.13um CMOS features. It gets kind of complicated, but in short, due to impurities found in the gate dielectrics of the transistors, the theoretical maximum voltage before dielectric breakdown (the gates on the transistors blow) of ~2.00V is much lower, so your risking actual physical damage to your CPU on the gate level.

If you need a more detailed explanation I would be happy to post.
 
Yes please. If you want to post more detailed I would be happy to read it
 
penguinpoo said:
Yes please. If you want to post more detailed I would be happy to read it

Well before I start, how familiar are you with the basic structures on a MOSFET and some basic field theory, I'll try to keep things conceptual, but don't want to be overdetailed if you already know some stuff. :)
 
1.75v will put you treading on tender territory.

The chip could last for a few weeks or even months if you are
running 24/7. I personally would not recommend above 1.70v and I don't think that you will see much of a stability improvement anyway. The chips will actually loose performance as you increase the vcore above 1.73v.

IMHO - with having used 3-2.4b's and 2-2.53 C1 stepping chips.
 
Enigma422 said:


Well before I start, how familiar are you with the basic structures on a MOSFET and some basic field theory, I'll try to keep things conceptual, but don't want to be overdetailed if you already know some stuff. :)
In this area... nothing! But i like to learn and understand why things happen. Thanks, I greatly appreciate this. :)
 
I took a 2.0a up tyo 1.8v for about half an hour. It booted at 3.0Ghz. It never ran the same EVER again. It was dying a slow death for about 4 months and has since been replaced. This was with a very good water cooled system (unless temps are extreme there isn't much extra damage caused by heat).

Some people get away with it. I tried and failed - my new chip is @ stock voltage and will stay there...at least for a week or two. I can't stand to see the poor thing so cool.
 
Okay, where do I begin......Let me begin by stating how a MOSFET transistor works. The MOSFET or Metal Oxide Semiconductor Field Effect Transistors are the what makes up a CPU. They are basically very small on/off switches (that whole 0s and 1s thing).

There are there are four basic structures in a MOSFET. They can be seenhere. Now current is created when carriers, sub atomic quantum particles, move from source region to the drain region. These carriers are present in all semiconductor devices, but are more heavily concentrated in the source and drain regions. This is done during the fabrication of the MOSFET.

The problem is, that there is no path for the current to travel from the source to the drain when the device is off in the device shown. This is done by creating a channel between the source and drain by changing the electrical properties of the substrate below the gate. This channel is controlled by the gate and the amount of voltage applied across it. (The explanation on how the channel is created can get pretty technical so I will leave it out for now. Will post if you are really interested). This is why you sometimes have to increase the voltage when you are overclocking. The transistors are switching so fast that a proper channel cannot be created with the given voltage. Impurities and defects present during fabrication can affect the ability of the MOSFET to create a current channel.

Now as the name MOSFET states, it is a field effect transistor. This means that it is controlled by an electric field. This electric field is created by applying a voltage across the gate. It is this electric field that creates the channel between the source and drain because of its ability to change the electrical properties of the substrate below the gate.

the first three letters in MOSFET stand for metal oxide semiconductor. If you look at the gate structure, the gate is made of metal (in todays semiconductor devices it is made of polysilicon, but as devices get smaller the properties of metal start becoming better again, so it may move back to metal) then below it is the dielectric or oxide, then the semiconductor itself. The oxide is where the damage occurs if you apply to much voltage across the drain. All atoms are effected by electric fields in such a way that the electron cloud that surround the nucleus of the atom start pulling away from the nucleus. This creates a dipole structure. As you apply more voltage you make the electric field acting across the atoms in the oxide stronger. Eventually you get to a point where you will completely rip the electron cloud away from the nucleus, and you have dielectric breakdown. This in effect has destroyed the oxide between the metal or polysilicon and the silicon substrate and you can no longer create the channel in the substrate that makes the MOSFET work.

There is a relationship between oxide thickness and gate length. As you shrink the size of the gate length you make this oxide layer thinner making it more likely to breakdown and destroy the capacitive properties of the MOS structure. This is why AMD and Intel reduce voltage everytime they release a new smaller process. It's not to run the CPU cooler, its a side effect of moving to smaller technology.

In an ideal world the relationship above would give you about a 2V maximum voltage that can be applied across the gate for a 0.13um process. Unfortunately there are non-idealites in the world that can reduce the ability for the dielectric/oxide in the MOS struture to stand up to higher electric fields. This reduces the amount of voltage the transistors on your P4 can take before the atoms in the oxide give way and this is why the people who apply to much voltage across when overclocking and are using relatively high voltage get SNDS.

I hope I explained this clear enough for understanding. I am trying to fit what I learned in about 10 weeks in my Semiconductor Device Physics II class into one post. Any specific questions feel free to ask. Maybe it would be easier to answer if you have more specific questions. This was a general explantion, as best as I could fit into one post.
 
Very succinct explanation Enigma, thanks.

So in development of these microprocessors, engineers must test the limits of their gate designs. how is gate damage confirmed? Scanning electron microscope?
 
caboob said:
Very succinct explanation Enigma, thanks.

So in development of these microprocessors, engineers must test the limits of their gate designs. how is gate damage confirmed? Scanning electron microscope?

There is a mathematical relationship between gate capacitance, gate thickness, channel length, and the gate materials dielectric constant. This is used the calculate the theoretical maximum voltage that the gate can withstand before dielectric breakdown. There is an even longer formula that takes into account the effects of non-idealities, but since these non-idealities cannot be taken into account all the time (variations from die to die, wafer to wafer, etc.) I believe the voltage that engineers designate as the default voltage for a CPU is based on fault tolerance and statistical analysis and place that default value well within the necessary voltage to create a channel, but as far as possible from the theoretical max voltage.

Gate damage can be confirmed by looking at the C-V (Capacitance vs Voltage) family of curves of a MOSFET. I don't know if it could be physically seen even with an SEM but the electrical properties of testing will tell whether the gate has gone through breakdown or not.

[EDIT] Just looked through my electromagnetic fields book, took that class a year ago, but seems the term "dielectric breakdown" I have been using is wrong for the phenomenon I am describing. Instead it should be called the dielectric strength of the material.
Now for silicon dioxide aka glass aka your dielectric material between gate and silicon the dielectric strength is about 30MV/m. Now you may say that's pretty big, but remember that your voltage is being applied over a very very small area so the electric field lines are very closely spaced, thus very strong field and if you apply enough voltage you can go over 30MV/m in your chip.
 
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Enigma422

Great read. I have never seen this explained in such detail.

Why don't you put this in a new thread and maybe the mods would do a sticky for it. I think this could help many to understand why they should not move above the 1.70 vcore.
 
Yes very good. Thank you! Im now paranoid about taking a chip beyond 1.7V... Or for that matter Stock. I was considering seeing what the chip could do at 1.85V. No longer tho!
 
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