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lower timings, same bandwidth-doesnt make sense!

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flapperhead

Senior Member
Joined
Apr 27, 2002
Location
wash dc area
im still playing around with my 2.4c. so far ive gotten the memory up to 290 @ 3-4-4-8. just tonite i figured what the heck, lets see how far i can drop the timings . well lo and behold i can run the memory at 2.5-4-4-6. in my book that is a decent drop, but my bandwidth numbers stay the same as with 3-4-4-8 (about 6700). to make sure the mb didnt default i checked cpuz and it shows the lower timings.... what gives??? im stumped.. any ideas???
 
true in theory, but this is the first time ive ever gotten the same sandra scores with lower timings on ddr. i wonder if it has something to do with the memory contoller, ie. after a certain speed the timings dont work..
 
The unbuffered benchmark usually show the impact of the lower latencies better.

Also CAS and tRAS don't make that much difference on Intel scores... ..still you would expect it to make a small but noticeable difference. Getting the exact same score in Sandra is pretty rare even using the same FSB and timings:)

3DMark01, especially "lobby low" and "lobby high" is quite good for seeing improvements gained from lower latencies.

Br
hepp
 
ive just finished another test with my memory using the tighest timings possible 2-3-3-5 at 200 mhz and again at loosest 3-4-4-8. and again the scores are almost the same! im getting a slight increase with the tight timings on this test, but its small.im starting to wonder if latentcy and timings are more effective or more specific to certain types of ddr memory or have i found something weird with the ic7? has anyone else ever compared their memory bandwidth at say 200 mhz with 2-2-2- 5 timings and then again at loosest 3-4-4-8? and if so, was there a marked difference?how much difference? i am under the assumption that there is a big difference.. flapperconfused
 
Hi Flapper,

Don't have IC7 or even C/W and I never tried my ADATA PC4000 at low timings since I did not think they would accept them.
But I have some old sandra scores with different modules that might help to illustrate this.
Springdale chip without xAT, all are single banked 2x256.
FPU B/W scores:

FSB 200 1:1
===================Buff=|Unbuff
ADATA PC4000 | 3-4-4-8 | 4361 |
NANYA PC3200 | 3-3-3-8 | 4410 | 2352
OCZ PC3500LE | 2-2-2-6 | 4480 | 2625

FSB 275 5:4
OCZ PC3500LE | 2-3-3-6 |5857|2696
OCZ PC3500LE | 2-3-2-6 |5925|2875

FSB 280 5:4
OCZ PC3500LE | 2-3-3-6 |5962|2755
OCZ PC3500LE | 2-3-2-6 |6028|2924

FSB 280 3:2
NANYA PC3200 | 3-3-3-8 |5253|2246
OCZ PC3500LE | 2-2-2-6 |5503|2623

As you can see the buffered scores do not change that much
but the unbuffered shows a bigger difference.

I don't see this as proof that timings don't matter but as an indication that Sandra buffered score is not the best benchmark for checking the effect of latencies.

Try running e.g. Super PI or 3Dmark01 lobby low/high to verify your results

Here are some 3Dmark scores that I borrowed.
They are not mine but I believe they are genuine.
P4C800/2.4c/KHX3200/9800Pro
FSB=250
..................................Lobby low..Incr.......high.....Incr
1:1 2.5-4-4-7................... 257,8............. 112,6
5:4 2-2-2-5 ......................264,1..2.4%... 115,8...2,8%
1:1 2-3-3-6 ..................... 265,2..2.9%....117,2...4%
1:1 2-2-2-5 ......................272,5..5.8%....121,3...7,7%

Br
hepp
 
Latencies have a huge effect on realized memory subsystem performance, or "effective bandwidth" as you might term it. It is very hard to analyze bandwidth alone, as latencies will come into play any time your data objects are large enough to produce a high degree of row and column switching. The truth is the bandwidth is not truly changed by the latencies, but what we perceive as bandwidth is.

This is all really much ado about nothing though. The computer is not a device created to produce bandwidth. It is a device created to run programs. How well it does this in most cases is not hugely affected by raw bandwidth of the memory subsystem. There are exceptions to this rule, but in general both the effective latency characteristics of the memory subsystem along with the effective cpu power dwarf the effects of bandwidth on application perfromance.

Sandra buffered bandwidth is essentially just a lie, a lie that assumes we can actually realize the full potential bandwidth of a given memory type and speed, calculates what percentage of optimal performance it feels your memory subsystem operates at, and then multiplies the theoretical maximum by this percentage. As such is not a true performance metric, and should be essentially ignored. The unbuffered bandwidth figures are an actual measurement, where the buffered ones are a rating. And anyone who has read many of my posts knows how fond I am of ratings.

The important thing is to put any and all systhetic benchmark results in their proper context by comparing them to actual application performance. By doing this consistantly, you can develop an understanding of what synthetic benchmarks can tell you, and more importantly what they cannot. In this context bandwidth itself is shown to be a rather minor point, but as with any optimizing proceedure, if we can maximize bandwidth without paying other penalties (such as increased latencies) we produce an faster system as a whole.

Just like hard drive, cpu, video card, or basically any other PC performance area memory performance is the composite of the individual performance yielded in an essentially infinite variety of circumstances. It is difficult to place single-number values on such complex and variable quantities, even if the side of us that yearns for simplicity likes such attempts. So although the Sandra buffered bandwidth largely succeeds in removing the effects of latency upon the bandwidth figures, this is a pointless goal that moves further away from the real quantity to be maximized-application performance.
 
Speed_mechanic2's figures in the thread someone with bh5 chips please help with scores/speed are a lot more complete than my pathetic attempt above.

They shows what I mentioned, but did not have the figures to back up.

tRCD has the biggest impact followed by tRP whereas going from CAS 2 to 2,5 has little impact.
3 to 2,5 would have even less impact.
Your original observation that 2,5-4-4-6 show very little improvement over 3-4-4-8 might be relevant even if the Sandra buffered B/W score in itself is not.

Br
hepp
 
larva said:
Latencies have a huge effect on realized memory subsystem performance, or "effective bandwidth" as you might term it. It is very hard to analyze bandwidth alone, as latencies will come into play any time your data objects are large enough to produce a high degree of row and column switching. The truth is the bandwidth is not truly changed by the latencies, but what we perceive as bandwidth is.

This is all really much ado about nothing though. The computer is not a device created to produce bandwidth. It is a device created to run programs. How well it does this in most cases is not hugely affected by raw bandwidth of the memory subsystem. There are exceptions to this rule, but in general both the effective latency characteristics of the memory subsystem along with the effective cpu power dwarf the effects of bandwidth on application perfromance.

Sandra buffered bandwidth is essentially just a lie, a lie that assumes we can actually realize the full potential bandwidth of a given memory type and speed, calculates what percentage of optimal performance it feels your memory subsystem operates at, and then multiplies the theoretical maximum by this percentage. As such is not a true performance metric, and should be essentially ignored. The unbuffered bandwidth figures are an actual measurement, where the buffered ones are a rating. And anyone who has read many of my posts knows how fond I am of ratings.

The important thing is to put any and all systhetic benchmark results in their proper context by comparing them to actual application performance. By doing this consistantly, you can develop an understanding of what synthetic benchmarks can tell you, and more importantly what they cannot. In this context bandwidth itself is shown to be a rather minor point, but as with any optimizing proceedure, if we can maximize bandwidth without paying other penalties (such as increased latencies) we produce an faster system as a whole.

Just like hard drive, cpu, video card, or basically any other PC performance area memory performance is the composite of the individual performance yielded in an essentially infinite variety of circumstances. It is difficult to place single-number values on such complex and variable quantities, even if the side of us that yearns for simplicity likes such attempts. So although the Sandra buffered bandwidth largely succeeds in removing the effects of latency upon the bandwidth figures, this is a pointless goal that moves further away from the real quantity to be maximized-application performance.


im not looking to find any special insight or discovery with what im doing here.I just found it curious that i had little or no change in my memory bandwidth at different timings.that never happened to me before. so i decided to ask the members for a little info on how their ddr responds to different timings. i asked for info on bh5 cause thats what most of the guys are using.now if i was an engineer maybe i could make some sense of what seemed to be the unresponsiveness of my memory . but anyway i really appreciate all the info and welcome the input, cause if u dont ask u never learn..
 
I was trying to address that, but I guess I ddn't do it clearly enough. I felt my first response was a bit too short, I guess this one too long.

On a basic fundamental level, bandwidth is not dependant upon latency. The Sandra buffered test attempts to boil things down to this essentially theoretical level, but is doing so by assumptions that do no reflect the true working conditions and actual realized performance of the memory subsystem. So while it's relative independance from latency is fundamentally correct, trying to boil the memory subsystem's performance into the basic building block of bandwidth seperate from latency is not particularly useful analysis. Effective performance as determined by bandwidth of the memory IC's themselves, the latencies they operate at, and the task being asked of them are of much more import.

In short, don't get too worried about buffered sandra results. Understanding the results requires some insight into the nature of the test itself, but secondary point is that truly understanding them is to realize that they simply need to be ignored.
 
flapperhead said:
ive just finished another test with my memory using the tighest timings possible 2-3-3-5 at 200 mhz and again at loosest 3-4-4-8. and again the scores are almost the same! im getting a slight increase with the tight timings on this test, but its small.im starting to wonder if latentcy and timings are more effective or more specific to certain types of ddr memory or have i found something weird with the ic7? has anyone else ever compared their memory bandwidth at say 200 mhz with 2-2-2- 5 timings and then again at loosest 3-4-4-8? and if so, was there a marked difference?how much difference? i am under the assumption that there is a big difference.. flapperconfused



I have found a bigger difference in latency with 3200 4000 mem running the same timings the 3200 is allot faster with whatever slow or the same timing i use, at the same speed. I have seen this all over the forms.

As far as bench score i have g-force 4600 agp 4x there is a big difference my system relies on system mem more to cram the agp 4x unbelievable difference that you can see and feel in game play and hard drive performance and multi tasking. 3200 2-2-2-5 rules compared to loose timing. with slower mem like when it's ready to be read or written to 2.5 3-3-7 even at 1/1 mem I got stalls and speed up and slow down in games. my games are perfect know fast and smooth all the time no stalls and when i use a certain key stroke or mouse button it does not miss any stroke of a key at all the only thing i changed was memory.
 
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