AMD road map info

theinquirer said:

current 130 nano Opterons will soon become dust.
AMD has started producing 90 nanometre versions of its 800, 200 and 100 series codenamed Athens, Troy and Venus. The Athlon MP is practically unobtainable now, and will exist for as long "as the market requires".

In the first half of next year, AMD will shift its FX and A64 chips to the San Diego, Venice and Palermo 90 nanometre SOI chips, displacing existing .13µ (micron) processors.

And during the first half of next year, it will introduce Lancaster, Newark and Georgetown notebook chips - these again will be based on 90 nanometre SOI cores, the first being a low voltage version.

In the second half of next year, we're promised a heap of dual core offerings.

In the Opteron market we'll see Egypt, Italy and Denmark - members of the 800, 200 and 100 series, built using 90 nanometre SOI technology.

On the desktop front, AMD will release the Toledo dual core chip.

On the notebook front the Roma 90 nano low voltage SOI microprocessor. It will also introduce Albany, a 90 nanometre SOI microprocessor. These chips don't appear to be dual core. µ

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hitechjb1 said:

From this article, from AMD presenation in the Fall Processor Forum, some dual-cores are 939-compatible.

http://www.extremetech.com/article2/0,1558,1666609,00.asp

"...Each dual-core chip will require about 205 million transistors, McGrath said. However, fabricating the chip in a 90-nm process will limit the die size to about that of a 130-nm Opteron; die size is a key determinant of a chip's cost. Finally, the dual-core chip will maintain socket compatibility with AMD's 939-pin processors, he said..."

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from above article said:

...
Each dual-core chip will require about 205 million transistors, McGrath said. However, fabricating the chip in a 90-nm process will limit the die size to about that of a 130-nm Opteron; die size is a key determinant of a chip's cost. Finally, the dual-core chip will maintain socket compatibility with AMD's 939-pin processors, he said.

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from above article said:

...
Performance-wise, the big news is the addition of SSE3 instructions, which accelerate a number of different types of computation, including video encoding, scientific computing, and software graphics vertex shaders. (For more on SSE3, see our Prescott review.) Beyond SSE3, the updated Hammer core will convert the LEA instruction, under certain circumstances, into an ADD instruction, which has only a single cycle of latency. AMD's design mavens have also added additional write-combining buffers to the chip, so it can combine up to four streams of non-cacheable writes, up from two. Hammer's data prefetch has been improved, as well.
...

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