Here's a brief thing I've been working on...it's a work in progress...forgive any errors.
What Does a CPU Do?
and
How Does It Do It?
Introduction The CPU, or central processing unit, of a computer, is often described as the computer's 'brain'. It would be perhaps better to describe it as a combination calculator and traffic policeman, since the CPU is responsible for performing most (if not all) of the computations that a modern computer requires, and is indeed the nerve center of the system.
The modern CPU is a complex device. The following is a bird's-eye view of how a CPU works, then commentary on modern desktop systems and their architecture. It is written from a computer-science standpoint and not an electrical engineer's standpoint--more information from the EE/CE perspective can be found in the fantastic posts by Hitechjb1 about the overclocking theory and practice of AMD processors.
Instructions in Memory and the Stored Program Concept Practically all modern computers store information as binary digits (bits) that are either one ('on') or zero ('off') organized into groups of eight (bytes). The theory behind the stored-program computer is that the programs that the computer runs can be saved into data memory in the same format as data itself, to be read back and executed at will. Instructions are stored as collections of bytes in the same memory that data are.
In binary, an instruction looks like this:
11110000 00001111 ...
which corresponds to a certain operation that a CPU is supposed to do, such as adding the contents of two
registers, or storing a register's content to memory, or jumping to some far-off place. (The exact meaning will vary among different processor types; for those hackish types in audience, you may notice that the above is F0 0F, which corresponds to a certain halt-and-catch-fire instruction on the Pentium.)
There are many different types of instructions, and on the x86, they include (and as far as I know are not limited to) :
* Arithmetic instructions (add, subtract, multiply, divide, shift arithmetic)
* Logical operations (conjunction/AND, disjunction/OR, exclusive disjunction/XOR, negation/NOT, shift logical)
* Comparison instructions (to set condition codes)
* Unconditional near and far jumps
* Conditional Branch (jump on condition codes)
* Conditional move (move if condition code)
* Move instructions (move register -> memory, register -> register, memory -> register, and push/pop to/from stack)
* Floating-point instructions (precise add/sub/mult/div, square root, trigonometric, exponentials, logarithms), and
* SIMD (Same Instruction Multiple Data) instructions that operate on groups of data.
* Special instructions (for instance, cause such-and-such interrupt, call procedure, return from procedure, flush caches, ...)
To make it even worse, there are prefixes, overrides, and all sorts of weird, wonky things that you can do with the x86
Registers and Addressing Modes A
register is a place where an operand for an instruction is stored, and is on the CPU die itself, and therefore quite quick to access. There are two types (generally) of registers--data registers, and address/pointer registers. Data registers, naturally, contain data that are operands for instruction. Address or pointer registers contain locations in memory that are referenced by instructions.
The segment register is a special class of address register. A 'segment' is a contiguous section of memory, usually assigned to a single task. Segmentation on the Intel x86 is both a genius and insane way of handling more memory than the original 16-bit address registers could handle. In the x86, the 16-bit segment registers are shifted left by a varying amount up to and including four bits, effectively performing a multiplication by a power of two, and then
added to the pointer register, resulting in a physical address. Segments on the x86 may overlap as a result.
Operands can be of many formats on the x86, few of which are simple. Due to backward compatibility, the addressing modes include and certainly aren't limited to--
* Word register <- Word register op immediate
* Word register <- Word register op 16-bit memory location
* Double-word register <- d.word register op immediate
* Memory doubleword <- Mem double op immediate
...
I would go on, but I'm not working for Intel.
General Architecture The Intel Pentium 4 and AMD Athlon (Note: I will speak about 32-bit architectures here, and then talk about the main differences between 32- and 64-bit) processors are the latest members of the 80x86 family, which in turn owe some of their heritage all the way back to the i4004 microcontroller.
The x86 processor as we PC users know it first appeared in the IBM PC as the 8086. It was, admittedly, a primitive machine, but it has shaped the architecture of Intel or AMD processor since. The 8086 had a 8-bit data bus, and internal 16 bit data registers, no floating point unit, no memory protection, and could address relatively little memory. The 8088 was designed to be close enough to the 4004 so that the translation of programs could be done automatically.
The 286 served as an interim between the primitive 8086 and the modern 386, and included memory protection. But the 386 really was the first truly modern CPU in the x86 family. The 386 brought forth 32-bit addressing, allowing x86 platforms to address up to some four gigabytes of RAM, and provided features for separating applications from one another. We also got protected mode with the 286 and 386, which allowed proper multitasking (although it wasn't really until 2000-ish with the advent of Windows XP that mainstream OSes started taking advantadge of it), memory protection, and virtual memory.
The 486 brought us an on-chip 8KiB L1 cache and an integrated floating-point unit. In the past, the FPU was a separate die (in fact, a completely separate unit), but the 486 brought it onboard. The 486 also made the x86 something more of a general purpose register machine, rather than the somewhat special-purpose-register machine that it had been.
The Pentium (P5) gave us superscalar execution (two pipelines, allowing the simultaneous execution of two instructions), branch prediction and speculative execution, SIMD with the MMX generation of Pentiums, and glueless two-way symmetric multiprocessing. (The Pentium was not called the 586 simply because one cannot trademark a number.)
The Pentium Pro gave the Pentium line an onboard Level 2 cache of 256K. The Pentium II is a Pentium Pro with a slightly different cache implementation. Between the PII and PIV, Intel added several more instruction set extensions including SSE/SSE2/SSE3.
Code from earlier x86 processors can, for the most part, be run on later generations. The backward-compatibility of the x86 is both its best and worst feature, and has allowed AMD and Intel to keep at the top of the CPU market. It has also forced Intel and AMD to keep a complex instruction set in place, and to keep extending it.
All this history brings us to today's Pentium 4 and AMD Athlons (as well as the Pentium D, by slight extension, and the Athlon64 by slight extension). Today's P4 has:
* Several 32-bit general purpose registers (EAX, EBX, ECX, EDX, ESI, EBP, ESP, EDP)
* Several 16-bit
segment registers (CS, DS, ES, FS, SS, GS)
* A 32-bit status register (EFLAGS)
* A 32-bit instruction pointer (EIP), which stores (a part of) the address of the next instruction to be executed
* A bunch of condition/control (CRn) registers, test registers (DRn), and floating-point registers
* Several MMX and SSE registers, for same-instruction-multiple-data (SIMD) operations.
It should be noted that the P4 does a LOT of internal voodoo and may have far more registers than Intel admits to in order to increase performance...however, none of these are directly usable by programs.
Registers - General Purpose Registers (GPRs) These registers may be used as a destination or source (operand) for any operation. Traditionally, the registers in the x86 have been used as special-purpose (with EAX being the accumulator, or destination for all operations, for instance). The eight GPRs handle many integer operations. Many branches are predicated upon the results of tests of general purpose registers. For what it's worth, Intel still advises caution when working with the ESP register (the stack pointer), which should not be used for anything but a pointer to the stack.
Registers - Segment Registers (SRs) Intel initially adopted an architecture that could only address a limited amount of memory. To (somewhat) step around this, they devised a plan that divided the address space into segments. This is why you will sometimes see the following notation, such as SS:ESP, which means (SS, shifted by some shift-amount) + the value in ESP. This enabled the older x86 processors to address more memory than 2^16 bytes, because the segment registers allowed one to select a particular segment of memory. Thankfully, this pain is somewhat dying out with flat addressing becoming somewhat more common. Restrictions: may not move to the code segment (CS) register, or pop to the CS register, as this will generate a General Protection Exception (usually).
Registers - Status/EFLAGS Register The EFLAGS register of the x86 contains a bunch of various bits and bobbles that are very important, such as the Interrupt Flag (which decides whether or not the processor can accept a software or hardware interrupt), condition codes (zero, carry, overflow, sign, parity, ...), several bits containing the input-output privelege level of the current program, a bit indicating whether or not the processor supports extended CPUID, and other various bobbles. Conditional branches in the x86 are largely based on the codes in this register. Conditional branches include jump if zero, jump if not zero, jump if above, jump if below, jump on carry, jump on overflow, jump on not carry, ... and so on. FLAGS is a special purpose register.
Registers - Instruction Pointer (EIP) Register The instruction pointer contains part of the address of the next instruction. When segments are in use, the full address of the next instruction is CS:EIP in 32-bit mode, CS:IP in 16-bit mode. Most modern OSes do away with segmentation entirely...resulting in flat 32-bit addressing. You may not write directly to the instruction pointer (for obvious reasons), and so jumps/branches/interrupts/returns are used to change the value of EIP.
(This is all I have...for now.)
