- Joined
- Jan 30, 2005
- Location
- Hove, Sussex, UK
Just a quick kinda techie rundown - but i've been looking at the HKEPC data that compares the C***** and the FX-62, and its obvious what AMD needs in the K8L to remain competitive.
First off, AMD currently has a 12 stage pipeline - C***** has a 12 to 14 stage - we cant be sure, but it looks like AMD dont need to change that at any rate. Maybe another 2 stages would give it a bit of a clockspeed boost and other architectural changes would make up for the increased length.
AMD has the upper hand in L1 cache size, although it needs to be waaay more associative - 2way vs 8way isnt much of a fair fight - even 4-way would be better!
C***** has an advantage as far as the L1 TLB's are concerned - the FX-62 has a combined total of 64 entries, Intel's offering has 384
The C***** has a slightly wider branch predictor compared to the FX-62, although i suspect AMD will be altering that in anycase, its only short by 4 bytes/cycle
Now we come to the big stuff, the proper internals.
First, the Load/Store units need a little improvement - namely AMD need to add one.
Secondly, the FPU and the SSE units on the FX-62 need to be improved. The C***** has a more complex FPU (from the looks of things), but SSE performance is absolutely gargantuan. Two 64-bit wide SSE units on the FX-62 just cannot compete with the three 128bit wide SSE units on the C*****.
Aside from those, the K8 architecture doesnt need to change anywhere near as radically as Intel has had to with the transition from Netburst to Core. The improvements that K8L will bring are still vague and unconfirmed, although if someone could take the data that i've used here:
http://translate.google.com/transla...&hl=en&ie=UTF-8&oe=UTF-8&prev=/language_tools
and add another column for the K8L specs (albeit speculative) - it could be interesting
First off, AMD currently has a 12 stage pipeline - C***** has a 12 to 14 stage - we cant be sure, but it looks like AMD dont need to change that at any rate. Maybe another 2 stages would give it a bit of a clockspeed boost and other architectural changes would make up for the increased length.
AMD has the upper hand in L1 cache size, although it needs to be waaay more associative - 2way vs 8way isnt much of a fair fight - even 4-way would be better!
C***** has an advantage as far as the L1 TLB's are concerned - the FX-62 has a combined total of 64 entries, Intel's offering has 384
The C***** has a slightly wider branch predictor compared to the FX-62, although i suspect AMD will be altering that in anycase, its only short by 4 bytes/cycle
Now we come to the big stuff, the proper internals.
First, the Load/Store units need a little improvement - namely AMD need to add one.
Secondly, the FPU and the SSE units on the FX-62 need to be improved. The C***** has a more complex FPU (from the looks of things), but SSE performance is absolutely gargantuan. Two 64-bit wide SSE units on the FX-62 just cannot compete with the three 128bit wide SSE units on the C*****.
Aside from those, the K8 architecture doesnt need to change anywhere near as radically as Intel has had to with the transition from Netburst to Core. The improvements that K8L will bring are still vague and unconfirmed, although if someone could take the data that i've used here:
http://translate.google.com/transla...&hl=en&ie=UTF-8&oe=UTF-8&prev=/language_tools
and add another column for the K8L specs (albeit speculative) - it could be interesting