[benbaked]

What makes the Core 2 Duo superior clock for clock to the Athlon 64/Opteron? They both have similar pipeline lengths (12 for A64/Opteron, 13 for C2D - is that correct?) and while Intel has the quad-pumped bus, AMD has HyperTransport. What is it exactly that makes the Core 2 Duo better, performance-wise?

[Brute Force]

Actually it is a 14 stage pipeline for the Core 2.

Here are other things that are superior to the K8 and Netburst architecture:

-An additional instruction set, oddly called SSE4 even though it has another codename already (NX or something like).

-Smaller die size than both the A64 and P4, as well as less transistors than the P4:

AMD Athlon 64 X2 (2x512KB) 90nm 154M 183 mm^2
Intel Core 2 65nm 291M 143 mm^2
Intel Pentium D 900 65nm 376M 162 mm^2

-Increased FSB to 266.5 MHz (X4=1066MHz, as well as 1333 for the Woodcrest).

And for the other technical stuff go here:

http://www.anandtech.com/cpuchipsets...oc.aspx?i=2748
http://xbitlabs.com/articles/cpu/dis...o-preview.html

[Maraxus]

wierd, i wonder how long till AMD brings out something that can keep up?

[UkJenT]

Weird, I could have sworn AMD was owning Intel Chips until Conroe came out.

[El<(')>Maxi]

They were with the exception of Dothan.

[Brute Force]

Originally Posted by El<(')>Maxi

They were with the exception of Dothan.

You mean Bonias.

[Hamm3r]

Core 2 also has wider pipeline, macro-ops fusion, single cycle SSE and other stuff.

[Sucka]

Originally Posted by Brute Force

You mean Bonias.

No he didn't. It's Banias, and Dothan was it's successor.

[Recursion]

Originally Posted by UkJenT

Weird, I could have sworn AMD was owning Intel Chips until Conroe came out.

we will not see a revamp of the X2 or Opteron line untill well late 2007 or early 2008

[dropadrop]

Actually AMD has stated they will demo the new quad (K8L) this year. It's still completly open when it will actually ship, my guess is not for quite a while. Also I have understood it will initially be a server chip, and they will make a dualcore version of it for consumer markets.

[hUMANbEATbOX]

i thought they were going to be showing quad core k8....k8l won't be seen for a while yet AFAIK.

[Recursion]

shjowing is one thing, he asked when we would be getting;

[hUMANbEATbOX]

Originally Posted by VincentP

shjowing is one thing, he asked when we would be getting;

who asked? my post was in response to dropadop

[Molester]

K8L by mid-07 latest, december this year earliest...the rumor of rev.G have quieted down and the thought is it the 65nm jump will be straight to K8L..

don't know why they would disregard the great yields on current architecture for 65nm quad-core..unless the K8L yields using SiGe are at least just as good and being on 300mm 65nm instead of 200mm 90nm, means more chips..not to mention counter Core2Duo...December will hold the answers..I don't see AMD making a "dumb" transition to ddr2 and then do a "dumb" shrink to 65nm...but that's my opinion.(by dumb, I mean, no other real improvements)

As for what makes Core2Duo so much better than Intel/Netburst and AMD/K8, it's the extra set of instructions, MUCH better fetch/pre-fetch, higher FSB due to better fetch/prefetch, large cache for the fetch/pre-fetch to play with, and 65nm process to allow for the large cache.

[benbaked]

Interesting.

But is any software taking advantage of SSE4 yet, or will be using SSE4 within the next two years? Surely within two years AMD will have adopted it.

Wouldn't 1066FSB be on par with HT running at 1000 MHz? The AMD should have better memory bandwidth anyways with the on-die controller.

The K8 design doesn't favor L2 cache that much, performance probably wouldn't increase if they adopted a 2x2 MB cache. Is the Conroe's L2 256-bits wide?

[Gnufsh]

Originally Posted by benbaked

Interesting.

But is any software taking advantage of SSE4 yet, or will be using SSE4 within the next two years? Surely within two years AMD will have adopted it.

That seems to be the way it usually works.

Wouldn't 1066FSB be on par with HT running at 1000 MHz? The AMD should have better memory bandwidth anyways with the on-die controller.

The 1066 is 64-bit while the HT link is 16-bit in each direction. So there is quite a differnece.

The K8 design doesn't favor L2 cache that much, performance probably wouldn't increase if they adopted a 2x2 MB cache. Is the Conroe's L2 256-bits wide?

I'm not sure off of the top of my head. The main advantages of conroe, if I remember correctly are improved branch prediction and it just being a wider core.