Question about AM2 buss width

OBLIVIONLORD · Aug 2, 2007

I understand that the Am2 uses its internal clock divided by half of the multi. However is the buss width 128bit within the Mem controller or how does it work?

If it is actually 128bit then the max throughput will only be 6,400gb/s

400 * 128 = 51200 / 8 = 6.4gb/s

http://www.digit-life.com/articles2/mainboard/ddr2-800-am2.html

"Even though this memory controller can provide the internal memory bus bandwidth on the level with the theoretical memory bandwidth of dual-channel DDR2 (from 6.4 GB/s for DDR2-400 to 12.8 GB/s for DDR2-800), the real data exchange rate between a processor and memory is limited to the bandwidth of FSB, which operates either at 200 MHz or at 266 MHz (in case of "extreme" CPU modifications). Its throughput is just 6.4 GB/s or 8.53 GB/s — which does not exceed the theoretical bandwidth of dual-channel DDR2-533 memory at best."

aaa · Aug 2, 2007

Which bus now? Half the multi?

I'm pretty sure the memory is 128bit.

OBLIVIONLORD · Aug 2, 2007

"Instead of being generated thru the CPU base clock (HTT clock, which is of 200 MHz), it divides the CPU internal clock. The value of this divider is half the value of the CPU multiplier."

http://www.hardwaresecrets.com/printpage/272/1

Kuroimaho · Aug 2, 2007

Right that's what I also noticed while playing with my proc.
Depends on clockspeed and multi only.

aaa · Aug 2, 2007

OBLIVIONLORD said:
400 * 128 = 51200 / 8 = 6.4gb/s

It's DDR. As in, Double Data Rate. There should be a multiply by two in there.

savageseb · Aug 2, 2007

aaa said:
It's DDR. As in, Double Data Rate. There should be a multiply by two in there.

the 2 you talk about has already been accounted for by the 400, it is 200*2

aaa · Aug 3, 2007

savageseb said:
the 2 you talk about has already been accounted for by the 400, it is 200*2

We're talkin AM2. With DDR2-800. As the 'max supported'.

mortimer · Aug 3, 2007

savageseb said:
the 2 you talk about has already been accounted for by the 400, it is 200*2

Don't think that it has. I'm running at 494*2. DDR2 adds another 2x. Whether its really any faster as latencies are a lot higher is another question.

aaa · Aug 3, 2007

mortimer said:
Don't think that it has. I'm running at 494*2. DDR2 adds another 2x. Whether its really any faster as latencies are a lot higher is another question.

Of course it's faster. Latency matters of course, but after that wait the data comes out at twice the speed of DDR1. Then there's the fact that 400 real mhz at CL4 is exactly the same latency as 200 real mhz at CL2 (count the nanoseconds). And isn't there (rare) CL3 DDR2-800? That would be lower latency than DDR1 ever was.

QuietIce · Aug 3, 2007

OBLIVIONLORD said:
http://www.digit-life.com/articles2/mainboard/ddr2-800-am2.html

"Even though this memory controller can provide the internal memory bus bandwidth on the level with the theoretical memory bandwidth of dual-channel DDR2 (from 6.4 GB/s for DDR2-400 to 12.8 GB/s for DDR2-800), the real data exchange rate between a processor and memory is limited to the bandwidth of FSB, which operates either at 200 MHz or at 266 MHz (in case of "extreme" CPU modifications). Its throughput is just 6.4 GB/s or 8.53 GB/s — which does not exceed the theoretical bandwidth of dual-channel DDR2-533 memory at best."

This is how INTEL handles memory, not AMD.

OBLIVIONLORD said:
"Instead of being generated thru the CPU base clock (HTT clock, which is of 200 MHz), it divides the CPU internal clock. The value of this divider is half the value of the CPU multiplier."

http://www.hardwaresecrets.com/printpage/272/1

For AMD DDR2 systems (AM2/AM2+) this is correct. However, BIOS's use different ways to express the MemLimit - some are "400" for full speed (1:1), some are "800" for full speed just as DDR (939/940) BIOS's use both "200" and "400" to mean 1:1. Either way the 1:1 setting is running DDR2-800 on AM2 regardless of the BIOS representation (just as 1:1 is DDR-400 on 939/940).

But unlike DDR, the DDR2 memory clock is double the "reference" clock (or "FSB"), 400 MHz instead of 200 MHz at stock, which is why the divider is only half the CPU multiplier instead of the whole CPU multiplier as it is with DDR. The extra doubling of both types of memory (to DDR2-800 and DDR-400, respectively) comes from the "DDR" designation, which means "Double Data Rate". Both DDR2 and DDR use the "top" and "bottom" of the memory clock cycle - they send two packets of data per clock cycle instead of just one. So DDR2, with a stock MemClock of 400 MHz, is DDR2-800 and DDR, with a stock MemClock of 200 MHz, is DDR-400.

One more note - the DDR2 MemClock runs slightly less than 400 (at stock) on odd CPU multipliers. The reason is the formula for calculating the actual MemClock, which is (CPU speed/MemDivider). The MemDivider for DDR2 (at 1:1) is half the CPU multiplier but must always be an integer and rounded up. So the MemDivider for an x13 CPU is 13/2=7, therefore a CPU running 2600 MHz (200x13) will only have MemClock of (2600/7) ~371 MHz, which doubles to DDR2-743 instead of DDR2-800 ...

OBLIVIONLORD · Aug 3, 2007

QuietIce said:
This is how INTEL handles memory, not AMD.
For AMD DDR2 systems (AM2/AM2+) this is correct. However, BIOS's use different ways to express the MemLimit - some are "400" for full speed (1:1), some are "800" for full speed just as DDR (939/940) BIOS's use both "200" and "400" to mean 1:1. Either way the 1:1 setting is running DDR2-800 on AM2 regardless of the BIOS representation (just as 1:1 is DDR-400 on 939/940).

But unlike DDR, the DDR2 memory clock is double the "reference" clock (or "FSB"), 400 MHz instead of 200 MHz at stock, which is why the divider is only half the CPU multiplier instead of the whole CPU multiplier as it is with DDR. The extra doubling of both types of memory (to DDR2-800 and DDR-400, respectively) comes from the "DDR" designation, which means "Double Data Rate". Both DDR2 and DDR use the "top" and "bottom" of the memory clock cycle - they send two packets of data per clock cycle instead of just one. So DDR2, with a stock MemClock of 400 MHz, is DDR2-800 and DDR, with a stock MemClock of 200 MHz, is DDR-400.

One more note - the DDR2 MemClock runs slightly less than 400 (at stock) on odd CPU multipliers. The reason is the formula for calculating the actual MemClock, which is (CPU speed/MemDivider). The MemDivider for DDR2 (at 1:1) is half the CPU multiplier but must always be an integer and rounded up. So the MemDivider for an x13 CPU is 13/2=7, therefore a CPU running 2600 MHz (200x13) will only have MemClock of (2600/7) ~371 MHz, which doubles to DDR2-743 instead of DDR2-800 ...

Well what Im getting at is that on Am2 chips the Mem Controller is only rated at 128bit DDR2 800 which is 12.8GB's. How is the full 12.8GB/s taking into account fully from the buss to the memcontroller, not the controller to the ram. The way I see it is this...

400 * 128 = 51200 / 8 = 6.4gb/s

Unless the 400mhz is actually DDR which would then answer my question however I can't find a single document from AMD anywhere mentioning it. If there is some form of refrence then that would be great however as it stands .. I'm left to assumptions that it may or may not.

aaa · Aug 3, 2007

OBLIVIONLORD said:
Well what Im getting at is that on Am2 chips the Mem Controller is only rated at 128bit DDR2 800 which is 12.8GB's. How is the full 12.8GB/s taking into account fully from the buss to the memcontroller, not the controller to the ram. The way I see it is this...

400 * 128 = 51200 / 8 = 6.4gb/s

Unless the 400mhz is actually DDR which would then answer my question however I can't find a single document from AMD anywhere mentioning it. If there is some form of refrence then that would be great however as it stands .. I'm left to assumptions that it may or may not.

It's an integrated memory controller. There is no bus from the controller to the cpu, it's part of the cpu. So there is no 400 of which you speak of.

OBLIVIONLORD · Aug 3, 2007

aaa said:
It's an integrated memory controller. There is no bus from the controller to the cpu, it's part of the cpu. So there is no 400 of which you speak of.

How does the cpu communicate to the mem controller exactly?

QuietIce · Aug 3, 2007

OBLIVIONLORD said:
How does the cpu communicate to the mem controller exactly?

The cores are connected to each other and the Crossbar through the System Request Interface (SRI). The Crossbar then connects to the memory controller and the HT Link. I couldn't find a good block diagram of the AM2 X2 with those details in it but here's the AMD page for the AM2 X2 showing 12.8GB/s: http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_9485_13041^13043,00.html

The block diagram represents everything on the CPU except the SRI and Crossbar ...

OBLIVIONLORD · Aug 3, 2007

I've read that already and it's not really what I'm looking for however I found a site.....

http://images10.newegg.com/UploadFilesForNewegg/itemintelligence/AMD/Dual Core Arch.pdf

Apparently there is somthing called a crossbar that connects the cpu with the Hypertransport and Mem Controller.

If this is also on AM2 chips then do you have any documents on that?

AlabamaCajun · Aug 3, 2007

Wow, I missed this thread. I saw the questions about where is the 2X for DDR2 and the answer that is in the dimms themselves as they are multiplexed into pairs and DRAM arrays. The multiplexers run at twice the DRAM speed then double data rate applies in the actual transfer. The 2X comes in the Dual Channel where the front end to the DRAM controller is 256bits wide multiplexed to 128. This would raise it to the theoretical 12.8Gbs but it was concluded that reality is it's only about 6-7Gbs real world!

AMD states the crossbar runs at 14GBs for Athlon 939 and 20GBs for Athlon AM2, and 22GBs for Opteron Step E and higher for Step F. Is it also possible the internal bus is 256bits wide?

aaa · Aug 3, 2007

OBLIVIONLORD said:
I've read that already and it's not really what I'm looking for however I found a site.....

http://images10.newegg.com/UploadFilesForNewegg/itemintelligence/AMD/Dual Core Arch.pdf

Apparently there is somthing called a crossbar that connects the cpu with the Hypertransport and Mem Controller.

If this is also on AM2 chips then do you have any documents on that?

This:
http://studies.ac.upc.edu/ETSETB/SEGPAR/microprocessors/amdk8 (mpr).pdf

Covers 754 though, with 64-bit memory width.

QuietIce · Aug 3, 2007

OBLIVIONLORD said:
I've read that already and it's not really what I'm looking for however I found a site.....

http://images10.newegg.com/UploadFilesForNewegg/itemintelligence/AMD/Dual Core Arch.pdf

Apparently there is somthing called a crossbar that connects the cpu with the Hypertransport and Mem Controller.

If this is also on AM2 chips then do you have any documents on that?

The only pic I found on the AMD site is in the AM2 Turion data - it shows the X-bar and DDR2 memory controller. But the Turion cannot, as yet, handle DDR2-800 speeds (only up to DDR2-667 according to the pic I found, which may be old), no doubt because of the power restraints on a mobile CPU. The block diagram for the Turion is exactly the same as the one you linked except for the numbers at the end of the Memory Controller arrows - they reflect the increased speeds of DDR2. But the earlier data I linked DOES show the DDR2-800 speeds from the X2 processor. I'm sure the internals are the same.

Edit: Aha! http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_8796_14309,00.html

PS: I'll send you a bill for the finder's fee!

AlabamaCajun said:
Wow, I missed this thread. I saw the questions about where is the 2X for DDR2 and the answer that is in the dimms themselves as they are multiplexed into pairs and DRAM arrays. The multiplexers run at twice the DRAM speed then double data rate applies in the actual transfer. The 2X comes in the Dual Channel where the front end to the DRAM controller is 256bits wide multiplexed to 128. This would raise it to the theoretical 12.8Gbs but it was concluded that reality is it's only about 6-7Gbs real world!

AMD states the crossbar runs at 14MBs for Athlon and 22MBs for Opteron. Is it also possible the internal bus is 256bits wide?

Uh, did you mean, "AMD states the crossbar runs at 14GBs for Athlon and 22GBs for Opteron. Is it also possible the internal bus is 256bits wide?"

Actually, I think somewhere in all the papers I've read they state the internal bus is 256 but I couldn't tell you where.

It may only be the "true" Opterons (or with "F" I guess it's all of them? - I haven't kept up on the new sockets) that has the higher X-bar speed (not the 939 Opty's) and probably because they run three HT Links instead of one (as you pointed out to me awhile back

) ...

OBLIVIONLORD · Aug 3, 2007

are there any documents showing the bit of the crossbar?

If the memcontroller is 256bit multiplexed to 128 then that basicly means that both streams can only be sent at a max of 128bit making a bottleneck or somthing?

AlabamaCajun · Aug 3, 2007

After looking at the links this is what "I think" is the internal layout of the bus(s).
Ram path is 128b per channel then more than like all the paths to the L2 cache is 128b. The crossbar is a different animal so I can't say for sure how it's arranged but I saw is somewhere but sure though. Code and Data are separated into two L1 caches according to operations where data is in one, pre-decoded instructions into the other. All operations internal to the processor are 64bits so it make sense that L1 and it's paths are 64b also. This gets a little tricky on the instruction side as we are dealing with pipelining of code making it difficult to determine.

Question about AM2 buss width

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