hahah
Harlam beat me to it, but i would like to make it its own thread.
http://www.xbitlabs.com/articles/cpu/display/amd-k10.html
so there are a lot of changes....
EDIT: and yet not a K8 with L3, but a k10 core baby.
FPU enhancements, Virtualization enhancements, New instructions for the FPU(bit population count, and leading zero count, remember? 1*10^n?) and SSE4 handling,
Side band stack optimizer for sequencing
"This way instructions working directly with the stack can be reordered without any limitations."
"So, faster stack operations decoding, Sideband Stack Optimizer unit, deeper return-address stack and successful prediction of indirect alternating branches make K10 much more efficient for processing of function-rich codes."
A better Branch prediction table....( i could go off mathematically here, hehe). A bigger cache for the TLB, etcetc...
Thank you L3, NUMA, and Floating point pipeline!
So intel faboys, read it and weep.
AMD fanboys rejoice.
if you dont care for the why or the how, go straight off to the conclusion.
"Substitute the words "Barcelona" or even "Phenom" for "Athlon 64 X2 6400+."
Amd 6400+ a phenom?
sure thing ed, sure thing. hehe
and as a bonus:
http://www.techarp.com/showarticle.aspx?artno=429&pgno=0
techarp is warning us to mark the calendar for announcements.
techarp talks with john Freude
http://techarp.com/showarticle.aspx?artno=434&pgno=0
Yaaaay!
Harlam beat me to it, but i would like to make it its own thread.
http://www.xbitlabs.com/articles/cpu/display/amd-k10.html
so there are a lot of changes....
EDIT: and yet not a K8 with L3, but a k10 core baby.
FPU enhancements, Virtualization enhancements, New instructions for the FPU(bit population count, and leading zero count, remember? 1*10^n?) and SSE4 handling,
Side band stack optimizer for sequencing
"This way instructions working directly with the stack can be reordered without any limitations."
"So, faster stack operations decoding, Sideband Stack Optimizer unit, deeper return-address stack and successful prediction of indirect alternating branches make K10 much more efficient for processing of function-rich codes."
A better Branch prediction table....( i could go off mathematically here, hehe). A bigger cache for the TLB, etcetc...
Thank you L3, NUMA, and Floating point pipeline!
So intel faboys, read it and weep.
AMD fanboys rejoice.
if you dont care for the why or the how, go straight off to the conclusion.
"Substitute the words "Barcelona" or even "Phenom" for "Athlon 64 X2 6400+."
Amd 6400+ a phenom?
sure thing ed, sure thing. hehe
and as a bonus:
http://www.techarp.com/showarticle.aspx?artno=429&pgno=0
techarp is warning us to mark the calendar for announcements.
techarp talks with john Freude
http://techarp.com/showarticle.aspx?artno=434&pgno=0
Yaaaay!
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