- Joined
- Aug 5, 2002
- Location
- Brisbane, Australia
Thanks to folks at G.Skill got a new DDR2 kit of memory to play with - 2x1GB G.Skill F2-8500CL5D-2GBPK 8 layer PCB dual channel kit. All that I have been told is that these use non-Micron D9 ICs but not sure what they use but they seem to perform very well so far.
System
Click image for larger screenshot
System
- Intel Core 2 Duo E8500 Q740A493T 2L7**** / **1808
- CPU Cooling: Corsair Nautilus 500 H20
- DFI LP LT X38-T2R 1/11 official bios
- 128MB Gainward FX5200 PCI
- 2x1GB G.Skill F2-8500CL5D-2GBPK 8 Layer PCB dual channel kit
- 750GB Samsung HD753LJ
- Pioneer DVD-RW
- 620W Corsair HX620 PSU
- WinXP Pro SP2
@533Mhz 5-5-5-15 at 2.00v bios (1.93-1.95v Smartguardian)
Click image for larger screenshot
Super Pi single & dual 32M
Everest Ultimate Bandwidth & SPD
Prime95 v25.6 Blend Load
DFI LP LT X38-T2R 1/11 Official Bios Settings
Code:
[B]PC Health Status[/B]
Adjust CPU Temp: +9
[B]CPU Feature[/B]
- Thermal Management Control: Disabled
- PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled
Exist Setup Shutdown: Mode 2
Shutdown after AC Loss: Disabled
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio: 9.5x
- Target CPU Clock: 3375
CPU N/2 Ratio: Enabled
CPU Clock: 355
Boot Up Clock: AUTO
DRAM Speed: 266/800
- Target DRAM Speed: 1067
PCIE Clock: 100mhz
PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled
[B]Voltage Settings[/B]
CPU VID Control: 1.1875v
CPU VID Special Add: AUTO
DRAM Voltage Control: 2.00v
SB Core/CPU PLL Voltage: 1.51
NB Core Voltage: 1.530
CPU VTT Voltage: 1.200
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110
[B]DRAM Timing[/B]
- Enhance Data transmitting: FAST
- Enhance Addressing: FAST
- T2 Dispatch: Enabled
[B]Clock Setting Fine Delay[/B]
Ch1 Clock Crossing Setting: More Aggressive
- DIMM 1 Clock fine delay: Current 89
- DIMM 2 Clock fine delay: Current 456
- DIMM 1 Control fine delay: Current 534
- DIMM 2 Control fine delay: Current 289
- Ch 1 Command fine delay: Current 801
Ch2 Clock Crossing Setting: More Aggressive
- DIMM 3 Clock fine delay: Current 89
- DIMM 4 Clock fine delay: Current 400
- DIMM 3 Control fine delay: Current 387
- DIMM 4 Control fine delay: Current 356
- Ch 2 Command fine delay: Current 801
Ch1Ch2 CommonClock Setting: More Aggressive
Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto
Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING)
CAS Latency Time (tCL): 5
RAS# to CAS# Delay (tRCD): 5
RAS# Precharge (tRP): 5
Precharge Delay (tRAS): 15
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): 42
Performance LVL (Read Delay) (tRD): AUTO
[B]Read delay phase adjust: Enter[/B]
Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: AUTO
- Channel 1 Phase 1 Pull-In: AUTO
- Channel 1 Phase 2 Pull-In: AUTO
- Channel 1 Phase 3 Pull-In: AUTO
- Channel 1 Phase 4 Pull-In: AUTO
Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto
MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): AUTO
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO
