Could AMD to Hyperthreading

I was wondering, with all this talk of neha and hyperthreading, could AMD implement a similar technology and put it under a different name. Or has Intel prettymuch patented it so heavily that AMD can't get to it.

IIRC, under their crosslicensing agreement, there's no reason why AMD couldn't apart from an enginnering and monetary standpoint. Hyperthreading isn't going to save AMD so they're probably diverting fungs and engineers to projects they deem more useful.

^It's not like AMD could "cross-license" everything they would happen to want from Intel.

i dont think it would be useful to them, they need a better architecture first.

SMT is a very power effective way to get performance, and AMD has the memory system to do it, but it requires good branch predictors and verification so I've read. I don't think AMD want to risk anything right now given their financial situation.

SMT would put AMD and Intel on equal footing with upcoming Nehalem as both have pretty much the same architecture with a point-to-point interconnect, a integrated memory controller, and a multicore processor in one package.

I think is AMD gets into SMT beyond the current MC solutions, it will be some sort of Hybrid proc that allows shared cache and closely linked cores.

Sure they can do it, look at what Sun is doing with Niagara and Microsoft did with the Xenon. I think it's a cheap way to improve efficiency and boost multi thread processing. No sense in not using it right now unless someone comes up with a way to get past 5GHz on air without sucking more juice than an air conditioner.

Any CPU MFG can but its best if AMD don't. HyperT is only used to extract more performance on a weak core as a temporary cheap replacement for an additional core or in a strong IPC core which has more potential that is not being utilized by software so it increases the CPUs SIMD/Instruction level parallelism per clock cycle and thus you obtain more performance. The best and main route forward for AMD is to increase prefetch algorithm speed and efficiency, increase cache speeds and sizes separately for server (smaller L2/fully associative large L3) and desktop (larger L2/smaller L3), decrease branch misprediction penalties, integer instruction latencies and and make a core that is efficient for the current software models around. Their highest weakness is SSSE additions which boost gaming/multimedia execution and latencies by a large margin, 3-4x. Once they have that instruction execution pathway for such code, they will be very close to onpar already if not ahead.