[CompuTamer]

I've been wondering this for a while now. I see C2D chips that have a "high" multi of 12, and then i think of my i7 that runs at a 21x multi. I'm not really complaining, as it makes it easy to OC, but why are the multipliers on iSeries processors so high?

[decoste007xt]

I think a higher multiplier for cpu power produces less heat and takes less power than a higher Bclk? Just my guess. Also since the Bclk is essentially what communicates with the rest of your PC they may not of wanted to stress the other parts at this stage in the game.

[Bobnova]

It's because of the low base frequency, using a 133 base makes for stronger easier to see timing signals, and also allows finer OCing for Turbo Boost (1x multi is only 133mhz instead of 333mhz).
The multi has to be high because the base is so low, that's the only reason.

The bclk itself is only a reference, nothing is transmitted over it like there is over FSB.
All the actual busses are are their own data pathways and their own clock signal that is based on the bclk clock signal.

[SecrtAgentMan]

I'd have to go with ^^ if anything, it seems like the most reasonable thing.

EDIT: Meant that towards decoste

[Jayws]

I believe that this has to do with the upcoming un-overclockable chips that apparently will have a FSB locked at 100 mhz. The only way to get to 3ghz with an FSB at 100 mhz is with a multi of 30.

[jason4207]

Originally Posted by Bobnova

It's because of the low base frequency, using a 133 base makes for stronger easier to see timing signals, and also allows finer OCing for Turbo Boost (1x multi is only 133mhz instead of 333mhz).
The multi has to be high because the base is so low, that's the only reason.

The bclk itself is only a reference, nothing is transmitted over it like there is over FSB.
All the actual busses are are their own data pathways and their own clock signal that is based on the bclk clock signal.

+1

It's all relative. If the reference clock signal is low the multi has to be high to get the CPU up to it's specified speed. If the reference clock signal is high then you only need a small multi.

The reference clock signals are chosen based on other factors besides final CPU speeds for the most part. On P4 and C2D/Q the reference signal is based on the FSB clock. FSB speeds increased over time, and as a result we saw multi's go down. Fortunately the newer chips were able to run at higher FSB speeds, and the chips themselves were also capable of higher speeds, so it all worked out, and overall CPU speeds increased over time along w/ the CPUs being able to do a lot more work per cycle. When the i-series hit there was no longer a FSB, and the reference signal is now called BCLK. The RAM, uncore, and CPU all use that signal and use an appropriate multi to get all the desired possible speed combinations needed for each sub-system. If the i-series used a higher BCLK signal then the number of possible RAM configurations would be lower and/or some kind of divider would have to be used which adds complexity.

When people say a chip has a high multi really what they mean is that the multi doesn't limit the OCability of the CPU. A lot of chips are said to be "FSB limited" which means using the max multi you reach the limits of the FSB/BCLK speed before you reach the limits of the CPU cores; this is considered a low multi chip imo. A chip is said to have a high multi if people typically run it at something lower than the max multi...there is headroom there to make more subtle adjustments to RAM, etc as you can always lower the FSB/BCLK and use a higher multi if needed.

Basically, don't look at the absolute number of the multi to compare them to say what's high and what's low. You need to look at it from a relative perspective and see if the multi is limiting your options or if it's irrelevant.