pcie 3.0 does not use more lanes it transfers more bits per lane so it's backwards compatible.
here is the link on specifications.
http://www.pcisig.com/news_room/faqs/pcie3.0_faq/#EQ3
Q: How does the PCIe 3.0 8GT/s “double” the PCIe 2.0 5GT/s bit rate?
A: The PCIe 2.0 bit rate is specified at 5GT/s, but with the 20 percent performance overhead of the 8b/10b encoding scheme, the delivered bandwidth is actually 4Gbps. PCIe 3.0 removes the requirement for 8b/10b encoding and uses a more efficient 128b/130b encoding scheme instead. By removing this overhead, the interconnect bandwidth can be doubled to 8Gbps with the implementation of the PCIe 3.0 specification. This bandwidth is the same as an interconnect running at 10GT/s with the 8b/10b encoding overhead. In this way, the PCIe 3.0 specifications deliver the same effective bandwidth, but without the prohibitive penalties associated with 10GT/s signaling, such as PHY design complexity and increased silicon die size and power. The following table summarizes the bit rate and approximate bandwidths for the various generations of the PCIe architecture:
approximate bandwidths for the various generations of the PCIe architecture:
PCIe architecture Raw bit rate Interconnect bandwidth Bandwidth per lane per direction Total bandwidth for x16 link
PCIe 1.x 2.5GT/s 2Gbps ~250MB/s ~8GB/s
PCIe 2.x 5.0GT/s 4Gbps ~500MB/s ~16GB/s
PCIe 3.0 8.0GT/s 8Gbps ~1GB/s ~32GB/s
